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PDF ICS952004 Data sheet ( Hoja de datos )
| Número de pieza | ICS952004 | |
| Descripción | Programmable Timing Control Hub for P4 processor | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS952004 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS952004
Programmable Timing Control Hub™ for P4™ processor
Recommended Application:
SIS 645/650 style chipsets.
Output Features:
• 2 - Pairs of differential CPUCLKs (differential current mode)
• 1 - SDRAM @ 3.3V
• 8 - PCI @3.3V
• 2 - AGP @ 3.3V
• 2 - ZCLKs @ 3.3V
• 1- 48MHz, @3.3V fixed.
• 1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
• 3- REF @3.3V, 14.318MHz.
Features/Benefits:
• Selectable asynchronous/synchronous AGP, ZCLK and
PCI outputs
• Programmable output frequency, divider ratios, output rise/
falltime, output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system
if system malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• For PC133 SDRAM system use the ICS9179-16 as the
memory buffer.
• For DDR SDRAM system use the ICS93705 or
ICS93722 as the memory buffer.
• Uses external 14.318MHz crystal.
Pin Configuration
VDDREF
**FS0/REF0
**FS1/REF1
**FS2/REF2
GNDREF
X1
X2
GNDZ
ZCLK0
ZCLK1
VDDZ
*PCI_STOP#
VDDPCI
**FS3/PCICLK_F0
**FS4/PCICLK_F1
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDSD
47 SDRAM
46 GNDSD
45 CPU_STOP#*
44 CPUCLKT_1
43 CPUCLKC_1
42 VDDCPU
41 GNDCPU
40 CPUCLKT_0
39 CPUCLKC_0
38 IREF
37 GNDA
36 VDDA
35 SCLK
34 SDATA
33 PD#*/Vtt_PWRGD
32 GNDAGP
31 AGPCLK0
30 AGPCLK1
29 VDDAGP
28 VDDA48
27 48MHz
26 24_48MHz/MULTISEL*
25 GND48
48-Pin 300-mil SSOP
* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
Block Diagram
PLL2
X1 XTAL
X2 OSC
48MHz
/ 2 24_48MHz
REF (1:0)
2
Key Specifications:
• PCI - PCI output skew: < 500ps
• CPU - SDRAM output skew: < 1ns
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
• AGP - AGP output skew: <150ps
Functionality
Control
ZCLK
DIVDER
Bit 2 Bit 7 Bit 6 Bit 5 Bit 4 CPU SDRAM ZCLK AGP
FS4 FS3 FS2 FS1 FS0 (MHz)
0 0 0 0 0 66.67
0 0 0 0 1 100.00
0 0 0 1 0 100.00
0 0 0 1 1 100.00
0 0 1 0 0 100.00
(MHz)
66.67
100.00
200.00
133.33
150.00
(MHz)
66.67
66.67
66.67
66.67
60.00
(MHz)
66.67
66.67
66.67
66.67
60.00
PCI
(MHz)
33.33
33.33
33.33
33.33
30.00
SDATA
SCLK
FS (4:0)
PD#
PCI_STOP#
CPU_STOP#
MULTISEL
PD#/Vtt_PWRGD
Logic
Config.
Reg.
PCI
DIVDER
AGP
DIVDER
SDRAM
DIVDER
0 0 1 0 1 100.00 125.00 62.50 62.50 31.25
0 0 1 1 0 100.00 160.00 66.67 66.67 33.33
0 0 1 1 1 100.00 133.33 80.00 66.67 33.33
0 1 0 0 0 100.00 200.00 66.67 66.67 33.33
0 1 0 0 1 100.00 166.67 62.50 62.50 31.25
0 1 0 1 0 100.00 166.67 71.43 83.33 41.67
Power Groups
0 1 0 1 1 80.00 133.33 66.67 66.67 33.33
VDDCPU = CPU
0 1 1 0 0 80.00 133.33 66.67 66.67 33.33
VDDPCI = PCICLK_F, PCICLK
0 1 1 0 1 95.00 95.00 63.33 63.33 31.67
VDDSD = SDRAM
0 1 1 1 0 95.00 126.67 63.33 63.33 31.67
AVDD48 = 48MHz, 24MHz, fixed PLL
0 1 1 1 1 66.67 66.67 50.00 50.00 25.00
AVDD = Analog Core PLL
Note: For additional margin testing frequencies, refer to Byte 4
VDDAGP= AGP
VDDREF = Xtal, REF
VDDZ = ZCLK
Stop
0489C—12/10/04
2 CPUCLKT (1:0)
2 CPUCLKC (1:0)
ZCLK (1:0)
2
6 PCICLK (9:0)
PCICLK_F (1:0)
2
AGP (1:0)
2
SDRAM
I REF
1 page  
Integrated
Circuit
Systems, Inc.
ICS952004
Serial Configuration Command Bitmap
Bytes 0-3: Are reserved for external clock buffer.
Byte4: Functionality and Frequency Select Register (default = 0)
Bit
Bit 2
Bit 7:4
Bit 3
Bit 1
Bit 0
Description
Bit 2 Bit 7 Bit 6 Bit 5 Bit 4
FS4 FS3 FS2 FS1 FS0 CPU SDRAM ZCLK
0 0 0 0 0 66.67 66.67 66.67
000 0
1 100.00 100.00 66.67
0 0 0 1 0 100.00 200.00 66.67
0 0 0 1 1 100.00 133.33 66.67
00
10
0
00 10
1
0 0 1 1 0 100.00 160.00 66.67
0 0 1 1 1 100.00 133.33 80.00
0 1 0 0 0 100.00 200.00 66.67
0 10 0
1 100.00 166.67 62.50
0 1 0 1 0 100.00 166.67 71.43
0 10 1 1
0 110 0
0 110
1 95.00 95.00 63.33
0 1 1 1 0 95.00 126.67 63.33
0 11 1 1
1 0 0 0 0 105.00 140.00 70.00
10 0 0
1 100.90 100.90 67.27
1 0 0 1 0 108.00 144.00 72.00
1 0 0 1 1 100.90 134.53 67.27
10
10
0 112.00 149.33 74.67
10 1 0
1 133.33 100.00 66.67
1 0 1 1 0 133.33 133.33 66.67
1 0 1 1 1 133.33 166.67 66.67
1 1 0 0 0 100.00 133.00 80.00
1 10 0
1 100.00 100.00 80.00
1 1 0 1 0 100.00 166.67 83.33
1 10 1 1
1110
0 100.00 133.00 100.00
1110
1 100.00 100.00 100.00
1 1 1 1 0 100.00 166.67 100.00
111 1 1
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit , 2 7:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
AGP
PCI
66.67
33.33
66.67
33.33
66.67
33.33
66.67
33.33
(Reserved)
(Reserved)
66.67
33.33
66.67
33.33
66.67
33.33
62.50
31.25
83.33
41.67
(Reserved)
(Reserved)
63.33
31.67
63.33
31.67
(Reserved)
70.00
35.00
67.27
33.63
72.00
36.00
67.27
33.63
74.67
37.33
66.67
33.33
66.67
33.33
66.67
33.33
66.67
33.33
66.67
33.33
62.50
31.25
(Reserved)
66.67
33.33
66.67
33.33
62.50
31.25
(Reserved)
PWD
Spread Precentage
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
00000
+/- 0.25% Center Spread Note1
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0
0
0
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Note: PWD = Power-Up Default
Third party brands and names are the property of their respective owners.
5
5 Page 
Integrated
Circuit
Systems, Inc.
Byte 23: Output Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
-
-
47
27
26
4
3
2
PWD
0
1
1
1
1
1
1
1
Description
Iref Output Control
MULITSEL Readback
SDRAM
48MHz
24_48MHz
REF2
REF1
REF0
ICS952004
Third party brands and names are the property of their respective owners.
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ICS952004.PDF ] | |
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