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PDF ICS952302 Data sheet ( Hoja de datos )
| Número de pieza | ICS952302 | |
| Descripción | Frequency Generator for TransmetaTM | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS952302 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS9523 0 2
Frequency Generator for TransmetaTM EfficeonTM
Recommended Application:
Transmeta Efficion, ATi M6
Output Features:
• 3 - CPUs @ 3.3V including 1 free running
CPUCLK_F
• 7 - PCI @ 3.3V, including 4 free running PCICLK_F
• 1 - 27MHz clock @ 3.3V
• 2 - 48MHz clocks @ 3.3V
• 2 - REF clocks @3.3V
Features:
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz referience input or XTAL.
• Full Load Power consumption reduced >10%
compared to reference device
• Power management via SMBus
Key Specifications:
• CPU output jitter: < 250ps
• PCI output skew: < 250ps
• CPUT - PCI output skew: 1-3ns
• 27MHz Accuracy < 50ppm
• 48MHz Accuracy < 50ppm
Functionality
Byte 4b7
0
0
0
0
1
1
1
1
Byte 4b6
0
0
1
1
0
0
1
1
Byte 4b5
0
1
0
1
0
1
0
1
Spread
%
+/-0.3
+/-0.6
+/-0.25
+/-0.45
CENTER
-0.60%
-1.20% DOWN
-0.50%
-0.90%
Pin Configuration
VDDREF 1
REF0 2
GNDREF 3
X1 4
X2 5
VDDPCI 6
PCICLK_F0 7
PCICLK_F1 8
GNDPCI 9
PCICLK0 10
PCICLK1 11
PCICLK_F2 12
PCICLK_F3 13
VDDPCI 14
PCICLK2 15
GNDPCI 16
N/C 17
N/C 18
VDDCOR 19
PCI_STOP# 20
**PD# 21
GND48 22
SDATA 23
SCLK 24
48-TSSOP
* Internal Pull-Up Resistor
**No Diode Clamp to VDD
48 REF1
47 VDDCPU
46 N/C
45 CPUCLK0
44 GNDCPU
43 CPUCLK1
42 CPUCLK_F
41 CPU_STOP#
40 GND
39 N/C
38 OE*
37 N/C
36 VDD
35 N/C
34 VDD27
33 GND
32 27MHZ
31 N/C
30 N/C
29 N/C
28 GND48
27 VDD48
26 48MHZ_1
25 48MHZ_0
0957B—10/05/04
1 page  
ICS9523 0 2
SMBus Table: Spread Spectrum Control Register
Byte 4
Pin #
Name
Control
Function
Type
Bit 7
-
Spread Position
Center or Down SS
RW
Bit 6
-
SS1
Spread Bit 1
RW
Bit 5
-
SS2
Spread Bit 2
RW
Bit 4
-
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
Reserved
Reserved
Reserved
Reserved
SMBus Table: Control Register
Byte 5
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Control
Function
Type
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Table: Control Register
Byte 6
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
Control
Function
Type
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SMBus Table: Vendor & Revision ID Register
Byte 7
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control
Function
REVISION ID
VENDOR ID
Type
R
R
R
R
R
R
R
R
01
Center
Down
See SS Table
01
01
01
--
--
--
--
--
--
--
--
PWD
1
0
0
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
PWD
-
-
-
-
-
-
-
-
PWD
x
x
x
x
0
0
0
1
0957B—10/05/04
5
5 Page 
ICS9523 0 2
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up,
they act as input pins. The logic level (voltage) that is
present on these pins at this time is read and stored into
a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device
changes the mode of operations for these pins to an
output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used.With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary.The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
0957B—10/05/04
Programming
Header
Via to Gnd
Via to
VDD
2K W
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ICS952302.PDF ] | |
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