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PDF ICS952601 Data sheet ( Hoja de datos )
| Número de pieza | ICS952601 | |
| Descripción | Programmable Timing Control Hub for Next Gen P4 processor | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS952601 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS952601
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
CK409 clock, Intel Yellow Cover part
Output Features:
• 3 - 0.7V current-mode differential CPU pairs
• 1 - 0.7V current-mode differential SRC pair
• 7 - PCI (33MHz)
• 3 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 1 - DOT, 48MHz
• 2 - REF, 14.318MHz
• 4 - 3V66, 66.66MHz
• 1 - VCH/3V66, selectable 48MHz or 66MHz
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA.
• Supports spread spectrum modulation, 0 to -0.5%
down spread.
• Supports CPU clks up to 400MHz in test mode.
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning.
• Supports undriven differential CPU, SRC pair in PD#
and CPU_STOP# for power management.
Key Specifications:
• CPU/SRC outputs cycle-cycle jitter < 125ps
• 3V66 outputs cycle-cycle jitter < 250ps
• PCI outputs cycle-cycle jitter < 250ps
• CPU outputs skew: < 100ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
Functionality
CPU
B6b5 FS_A FS_B MHz
0 0 100
0 MID Ref/N0
0 0 1 200
1 0 133
1 1 166
1 MID Hi-Z
0 0 200
1
0
1
1 400
0 266
1 1 333
SRC
MHz
100/200
Ref/N1
100/200
100/200
100/200
Hi-Z
100/200
100/200
100/200
100/200
3V66 PCI
MHz MHz
66.66 33.33
Ref/N2 Ref/N3
66.66 33.33
66.66 33.33
66.66 33.33
Hi-Z Hi-Z
66.66 33.33
66.66 33.33
66.66 33.33
66.66 33.33
REF
MHz
14.318
Ref/N4
14.318
14.318
14.318
Hi-Z
14.318
14.318
14.318
14.318
USB/DOT
MHz
48.00
Ref/N5
48.00
48.00
48.00
Hi-Z
48.00
48.00
48.00
48.00
Pin Configuration
REF0 1
REF1 2
VDDREF 3
X1 4
X2 5
GND 6
PCICLK_F0 7
PCICLK_F1 8
PCICLK_F2 9
VDDPCI 10
GND 11
PCICLK0 12
PCICLK1 13
PCICLK2 14
PCICLK3 15
VDDPCI 16
GND 17
PCICLK4 18
PCICLK5 19
PCICLK6 20
PD# 21
3V66_0 22
3V66_1 23
VDD3V66 24
GND 25
3V66_2 26
3V66_3 27
SCLK 28
56 FS_B
55 VDDA
54 GNDA
53 GND
52 IREF
51 FS_A
50 CPU_STOP#
49 PCI_STOP#
48 VDDCPU
47 CPUCLKT2
46 CPUCLKC2
45 GND
44 CPUCLKT1
43 CPUCLKC1
42 VDDCPU
41 CPUCLKT0
40 CPUCLKC0
39 GND
38 SRCCLKT
37 SRCCLKC
36 VDD
35 Vtt_PWRGD#
34 VDD48
33 GND
32 48MHz_DOT
31 48MHz_USB
30 SDATA
29 3V66_4/VCH
56-pin SSOP & TSSOP
0701G—10/13/04
1 page  
Integrated
Circuit
Systems, Inc.
ICS952601
Absolute Max
Symbol
VDD_A
VDD_In
Ts
Tambient
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection human body model
Min
GND - 0.5
-65
0
2000
Max
VDD + 0.5V
VDD + 0.5V
150
70
115
Units
V
V
°C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Input High Voltage
Input MID Voltage
Input Low Voltage
Input High Current
Input Low Current
VIH
VMID
VIL
IIH
IIL1
IIL2
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
VIN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up
resistors
2
1
VSS - 0.3
-5
-5
-200
VDD + 0.3
1.8
0.8
5
V
V
V
uA
uA
uA
Operating Supply Current
IDD3.3OP
Full Active, CL = Full load;
258
Powerdown Current
IDD3.3PD
all diff pairs driven
all differential pairs tri-stated
29
0.3
Input Frequency3
Pin Inductance1
Fi
Lpin
VDD = 3.3 V
14.31818
Input Capacitance1
CIN
COUT
Logic Inputs
Output pin capacitance
CINX
X1 & X2 pins
Clk Stabilization1,2
TSTAB
From VDD Power-Up or de-
assertion of PD# to 1st clock
Modulation Frequency
Triangular Modulation
30
Tdrive_SRC
SRC output enable after
PCI_Stop# de-assertion
Tdrive_PD#
CPU output enable after
PD# de-assertion
Tfall_Pd#
PD# fall time of
Trise_Pd#
PD# rise time of
Tdrive_CPU_Stop#
CPU output enable after
CPU_Stop# de-assertion
Tfall_CPU_Stop#
PD# fall time of
Trise_CPU_Stop#
PD# rise time of
SMBus Voltage
VDD
2.7
Low-level Output Voltage
VOL
@ IPULLUP
Current sinking at VOL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time3
IPULLUP
TRI2C
4
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA
Clock/Data Fall Time3
TFI2C (Min VIH + 0.15) to (Max VIL - 0.15)
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
0701G—10/13/04
350
35
12
7
5
6
5
1.8
33
15
300
5
5
10
5
5
5.5
0.4
1000
300
mA
mA
mA
MHz
nH
pF
pF
pF
ms
kHz
ns
3
1
1
1
1
1,2
1
1
us 1
ns 1
ns 2
us 1
ns 1
ns 2
V1
V1
mA 1
ns 1
ns 1
5
5 Page 
Integrated
Circuit
Systems, Inc.
ICS952601
I2C Table: Read-Back Register
Byte 0
Bit 7
Bit 6
Pin #
-
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Name
RESERVED
RESERVED
RESERVED
RESERVED
PCI_STOP#
CPU_STOP#
FSB
FSA
Control Function
RESERVED
RESERVED
RESERVED
RESERVED
PCI STOP# Read
Back
CPU STOP Read
Back
Freq Select 1 Read
Back
Freq Select 0 Read
Back
Type
-
-
-
-
R
R
R
R
01
RESERVED
RESERVED
RESERVED
RESERVED
READBACK
READBACK
READBACK of CPU(2:0)
Frequency
PWD
X
X
X
X
X
X
X
X
I2C Table: Spreading and Device Behavior Control Register
Byte 1
Pin #
Name
Control Function
Bit 7
37,38
SRC/SRC#
SRC Free-Running
Control
Bit 6
37,38
SRC
Output Control
Bit 5
46,47
CPUT2/CPUC2
CPU FREE-
Bit 4
43,44
CPUT1/CPUC1
RUNNING
Bit 3
40,41
CPUT0/CPUC0
CONTROL
Bit 2
46,47
CPUT2/CPUC2
Output Control
Bit 1
43,44
CPUT1/CPUC1
Output Control
Bit 0
40,41
CPUT0/CPUC0
Output Enable
Type
RW
RW
RW
RW
RW
RW
RW
RW
01
FREE-RUN STOPPABLE
Disable
FREE-RUN
FREE-RUN
FREE-RUN
Disable
Disable
Disable
Enable
STOPPABLE
STOPPABLE
STOPPABLE
Enable
Enable
Enable
PWD
0
1
1
1
1
1
1
1
I2C Table: Output Control Register
Byte 2
Pin #
Name
Control Function Type
0
1 PWD
Bit 7
37,38
SRC_PD#
Drive Mode
0: Driven in PD#
RW
Driven
Hi-Z
0
Bit 6
37,38
SRC_Stop#
Drive Mode
0: Driven in
PCI_Stop#
RW Driven
Hi-Z
0
Bit 5
Bit 4
46,47
43,44
CPUT2_PD# Drive Mode
RW Driven
0:driven in PD#
CPUT1_PD# Drive Mode
1: Tri-stated
RW Driven
Hi-Z
Hi-Z
0
0
Bit 3
40,41
CPUT0_PD# Drive Mode
RW Driven
Hi-Z
0
Bit 2
Bit 1
Bit 0
46,47
43,44
40,41
CPUT2_Stop Drive Mode
CPUT1_Stop Drive Mode
CPUT0_Stop Drive Mode
0:driven when
stopped
1: Tri-stated
RW Driven
RW Driven
RW Driven
Hi-Z
Hi-Z
Hi-Z
0
0
0
0701G—10/13/04
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ICS952601.PDF ] | |
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