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PDF GS4982 Data sheet ( Hoja de datos )

Número de pieza GS4982
Descripción (GS4882 / GS4982) Video Sync Separators with 50% Sync Slicing
Fabricantes ETC 
Logotipo ETC Logotipo



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No Preview Available ! GS4982 Hoja de datos, Descripción, Manual

GS4882, GS4982 Video Sync
Separators with 50% Sync Slicing
FEATURES
• precision 50% sync slicing
• internal color burst filter
• ±5 ns temperature stability
• superior noise immunity
• robust signal detection/output muting circuitry
• high performance dual mode input clamp
• 0.5 V to 4.0 Vpp input signal with +5 V supply
• composite, vertical, back porch, odd/even outputs
• horizontal sync output available with GS4982
• +4.5 V to +13.2 V supply voltage range
• Pb-free and Green
ORDERING INFORMATION
Part Number
GS4882-CDA
GS4882-CKA
GS4882-CTA
GS4982-CDA
GS4982-CKA
GS4982-CTA
GS4882-CKAE3
GS4982-CKAE3
Package
Type
8 pin PDIP
Temperature
Range
0° C to 70° C
8 pin SOIC
0° C to 70° C
8 pin SOIC Tape 0° C to 70° C
8 pin PDIP
0° C to 70° C
8 pin SOIC
0° C to 70° C
8 pin SOIC Tape 0° C to 70° C
8 pin SOIC
0° C to 70° C
8 pin SOIC
0° C to 70° C
Pb-Free
and Green
No
No
No
No
No
No
Yes
Yes
DATA SHEET
DESCRIPTION
The GS4882 and GS4982 are precision sync separators for
extracting timing information from NTSC, PAL, and SECAM
video signals. The GS4882 generates noise immune and
temperature stable composite sync, vertical sync, back porch
and odd/even field signals. The GS4982 provides a horizontal
sync output for those applications requiring horizontal sync
extraction.
The GS4882 and GS4982 feature an internal color burst filter
for minimization of spurious timing information and the reduction
of external component count. The precision 50% sync slicing
feature embodied in the device provides for superior sync
extraction in the presence of noise and varying sync pulse
amplitudes. The high performance dual mode input clamp
aids in maintaining the accuracy of the internally derived 50%
sync slicing level to within ±5% as well in reducing system
start-up/recovery time. In addition, a missing pulse detector
enables the devices to quickly respond to impulse noise by
temporarily turning on a Nosync Recovery Current connected
to the dual mode input clamp. The input stage will operate with
input signal amplitudes ranging from +0.5 to +4.0V peak to
peak with a +5V supply voltage.
The GS4882 and GS4982 have robust signal detection and
output muting circuitry. Should valid video be removed from
the device input, the absence of video will be automatically
detected and all outputs muted to a logic high state after a
defined probation period. Upon the return of a valid video
signal, device outputs are enabled after receiving 8 lines of
video. An internal frequency to voltage converter also allows
the device to differentiate between valid and invalid input
signals by analyzing the horizontal scan rate of the input signal
and comparing it against the expected input signal scan rate.
The GS4882 and GS4982 are available in standard 8 pin PDIP
and SOIC packages, operate with a + 4.5 to +13.2 volt supply
voltage range and typically consume less than 6 mA of current
with a +5 V supply voltage.
PIN CONNECTIONS
GS4882
COMPOSITE
SYNC OUT
COMPOSITE
VIDEO IN
VERTICAL
SYNC OUT
GROUND
1
2
3
4
8
7
6
5
Vcc
ODD/EVEN
RSET
BACK PORCH
GS4982
HORIZONTAL
COMPOSITE
VIDEO IN
VERTICAL
SYNC OUT
GROUND
1
2
3
4
8
7
6
5
Vcc
ODD/EVEN
RSET
BACK PORCH
Revision date: July 2004
Patent Pending.
Document No. 521 - 61 - 01
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
Gennum Japan: Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo 160-0023 Japan Tel: +81 (03) 3349-5501 Fax: +81 (03) 3349-5505

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GS4982 pdf
SIGNAL DETECT AND OUTPUT MUTE
Internal to the GS4882 and GS4982 is a robust video signal
detection circuit. This circuit provides a reliable control signal
that will enable the sync separator outputs only when a valid
video signal is present. When the input signal is not valid, the
outputs are muted and stay in a logic high state.
The GS4882 and GS4982 differentiate between valid and in-
valid input signals by feeding the horizontal sync information
into a frequency to voltage converter. The horizontal scan rate
of the input signal is then compared to an expected input
signal horizontal scan rate. With RSET=227 k, the sync
separator will typically define a valid input signal as one with
a horizontal frequency of 15.7 ± 4 kHz.
Assuming that the sync separator is in steady state operation
with a valid input signal, all outputs will be enabled. Removal
of the input signal, or a significant change in the input signal
frequency, will cause an internal probation timer to be triggered.
While on probation, the sync separator outputs remain
enabled and separated sync is still produced. If a valid input
signal is not returned to the system before the probation time
expires (typically 2.5 ms), all outputs will be muted to logic
high state. Should a valid signal return during the probation
period, and eight lines be received before the probation time
expires, device outputs will remain enabled. Once device
outputs are muted, the device must receive 8 valid lines of
video at the correct horizontal frequency before the outputs
are re-enabled.
CLEN
+ VSC
-
CCLLAAMMPP
WWIINNDDOOWW
HORIZONTAL
-
COMPOSITE
SYNC OUTPUT
(Pin 1)
+
VIDEO
INPUT
(Pin 2)
0.1µ
-
+
2NDFIOLTREDRER
BBEESSSSEELL
2NFDILOTREDRER
-
+ VHC
IINNTTEEGGRRAATTEEDD
HHOOLLDD
50%
POINT
FFAAUULLTT
HHAANNDDLLIINNGG
VSC
R
R
WINDOWING
CIRCUIT
SIGNAL
DETECT
MUTE
DQ
GQ
DQ
CLK Q
ODD / EVEN
OUTPUT
(Pin 7)
NO SYNC
VCC
(Pin 8)
RSET
(Pin 6)
227k
VOLTAGE
REGULATOR
TIMING
CURRENTS
0.1µ
VERTICAL
DETECTOR
BACK PORCH
DETECTOR
DQ
CLK Q
BPEN
Fig. 6 GS4882 Block Diagram
VERTICAL SYNC
OUTPUT
(PIN 3)
BACK PORCH
OUTPUT
(Pin 5)
VIDEO
INPUT
(Pin 2)
0.1µ
-
+
CLEN
+ VSC
-
2ND ORDER
BESSEL
FILTER
-
+ VHC
NO SYNC
CLAMP
WINDOW
HORIZONTAL
-
+
INTEGRATED
HOLD
50%
POINT
FAULT
HANDLING
VSC
R
R
WINDOWING
CIRCUIT
HORIZONTAL
(Pin 1)
SIGNAL
DETECT
MUTE
DQ
GQ
DQ
CLK Q
ODD / EVEN
OUTPUT
(Pin 7)
VCC
(Pin 8)
RSET
(Pin 6)
227k
VOLTAGE
REGULATOR
TIMING
CURRENTS
0.1µ
VERTICAL
DETECTOR
BACK PORCH
DETECTOR
DQ
CLK Q
BPEN
Fig. 7 GS4982 Block Diagram
5 of 7
VERTICAL SYNC
OUTPUT
(PIN 3)
BACK PORCH
OUTPUT
(Pin 5)
521 - 61 - 01

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