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PDF DS2153Q Data sheet ( Hoja de datos )
| Número de pieza | DS2153Q | |
| Descripción | E1 Single-Chip Transceiver | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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DS2153Q
E1 Single-Chip Transceiver
FEATURES
Complete E1(CEPT) PCM-30/ISDN-PRI
transceiver functionality
Onboard line interface for clock/data recovery
and waveshaping
32-bit or 128-bit jitter attenuator
Generates line build-outs for both 120-ohm
and 75-ohm lines
Frames to FAS, CAS, and CRC4 formats
Dual onboard two-frame elastic store slip
buffers that can connect to backplanes up to
8.192 MHz
8-bit parallel control port that can be used on
either multiplexed or non-multiplexed buses
Extracts and inserts CAS signaling
Detects and generates Remote and AIS alarms
Programmable output clocks for Fractional
E1, H0, and H12 applications
Fully independent transmit and receive
functionality
Full access to both Si and Sa bits
Three separate loopbacks for testing
Large counters for bipolar and code
violations, CRC4 code word errors, FAS
errors, and E bits
Pin-compatible with DS2151Q T1 Single-
Chip Transceiver
5V supply; low power CMOS
Industrial grade version (-40°C to +85°C)
available (DS2153QN)
PIN ASSIGNMENT
FUNCTIONAL BLOCKS
PARALLEL CONTROL
PORT
DALLAS
DS2153Q
E1 SCT
ACTUAL SIZE OF 44-PIN PLCC
ALE
WR
RLINK
RLCLK
DVSS
RCLK
RCHCLK
RSER
RSYNC
RLOS/LOTC
SYSCLK
7
8
9
10
11
12
13
14
15
16
17
39 TSER
38 TCLK
37 DVDD
36 TSYNC
35 TLINK
34 TLCLK
33 TCHBLK
32 TRING
31 TVDD
30 TVSS
29 TTIP
DESCRIPTION
The DS2153Q T1 Single-Chip Transceiver (SCT) contains all of the necessary functions for connection
to E1 lines. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ
serial stream. The DS2153 automatically adjusts to E1 22 AWG (0.6 mm) twisted-pair cables from 0 to
1.5 km. The device can generate the necessary G.703 waveshapes for both 75-ohm and 120-ohm cables.
The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit
or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data
stream for alarms. It is also used for extracting and inserting signaling data, Si, and Sa-bit information.
The device contains a set of 71 8-bit internal registers which the user can access to control the operation
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070299
1 page  
PIN DESCRIPTION Table 1-1
DS2153Q
PIN SYMBOL TYPE
DESCRIPTION
1 AD4 I/O Address/Data Bus. An 8-bit multiplexed address/data bus.
2 AD5
3 AD6
4 AD7
5 RD (DS) I Read Input (Data Strobe).
6 CS
I Chip Select. Must be low to read or write the port.
7 ALE(AS)
I Address Latch Enable (Address Strobe). A positive going edge
serves to demultiplex the bus.
8 WR (R/ W ) I Write Input (Read/Write).
9 RLINK O Receive Link Data. Outputs the full receive data stream including
the Sa bits. See Section 13 for timing details.
10 RLCLK
O Receive Link Clock. 4 kHz to 20 kHz demand clock for the RLINK
output; controlled by RCR2. See Section 13 for timing details.
11 DVSS
- Digital Signal Ground. 0.0 volts. Should be tied to local ground
plane.
12 RCLK
O Receive Clock. Recovered 2.048 MHz clock.
13 RCHCLK
O Receive Channel Clock. 256 kHz clock which pulses high during
the LSB of each channel. Useful for parallel to serial conversion of
channel data. See Section 13 for timing details.
14 RSER
O Receive Serial Data. Received NRZ serial data, updated on rising
edges of RCLK or SYSCLK.
15 RSYNC I/O Receive Sync. An extracted pulse, one RCLK wide, is output at this
pin which identifies either frame (RCR1.6=0) or multiframe
boundaries (RCR1.6=1). If the elastic store is enabled via the
RCR2.1, then this pin can be enabled to be an input via RCR1.5 at
which a frame boundary pulse is applied. See Section 13 for timing
details.
16 RLOS/LOTC
O Receive Loss of Sync/Loss of Transmit Clock. A dual function
output. If TCR2.0=0, will toggle high when the synchronizer is
searching for the E1 frame and multiframe; if TCR2.0=1, will toggle
high if the TCLK pin has not toggled for 5 µs.
17 SYSCLK
I System Clock. 1.544 MHz or 2.048 MHz clock. Only used when
the elastic store functions are enabled via RCR2.1. Should be tied
low in applications that do not use the elastic store. If tied high for at
least 100 µs, will force all output pins (including the parallel port) to
3-state.
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5 Page 
RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)
(MSB)
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S RSCLKM RESE
DS2153Q
(LSB)
-
SYMBOL
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
RSCLKM
RESE
-
POSITION NAME AND DESCRIPTION
RCR2.7
Sa8 Bit Select. Set to 1 to report the Sa8 bit at the RLINK pin;
set to 0 to not report the Sa8 bit.
RCR2.6
Sa7 Bit Select. Set to 1to report the Sa7 bit at the RLINK pin;
set to 0 to not report the Sa7 bit.
RCR2.5
Sa6 Bit Select. Set to 1 to report the Sa6 bit at the RLINK pin;
set to 0 to not report the Sa6 bit.
RCR2.4
Sa5 Bit Select. Set to 1 to report the Sa5 bit at the RLINK pin;
set to 0 to not report the Sa5 bit.
RCR2.3
Sa4 Bit Select. Set to 1 to report the Sa4 bit at the RLINK pin;
set to 0 to not report the Sa4 bit.
RCR2.2
Receive Side SYSCLK Mode Select.
0=if SYSCLK is 1.544 MHz
1=if SYSCLK is 2.048 MHz
RCR2.1
Receive Side Elastic Store Enable.
0=elastic store is bypassed
1=elastic store is enabled
RCR2.0 Not Assigned. Should be set to 0 when written.
11 of 52
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| PDF Descargar | [ Datasheet DS2153Q.PDF ] | |
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