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PDF NHI1599ET Data sheet ( Hoja de datos )

Número de pieza NHI1599ET
Descripción (NHI Series) Multi-Protocol Data Bus Interface
Fabricantes National Hybrid 
Logotipo National Hybrid Logotipo



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www.DaNtaMSAhuNeTleHtti4IiU-POE.rcTooNmtoEAcnoLhlaDnHachteYadeBBeuTRtse4rIImnUDtien.,rcafIlaosncmec.Bus Controller, Remote Terminal, Bus Monitor
.DUasetra'sSManualVersion 2003.07.14
w July 2003
wThe information provided in this document is believed to be accurate; however, no responsibility is assumed by NATIONAL
HYBRID, INC. for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications
mare subject to change without notice.
w .co2200 Smithtown Avenue, Ronkonkoma, NY 11779
t4UTelephone (631) 981- 2400 Data Bus Fax (631) 981- 2445
www.DataSheeWebsite http: //www.nationalhybrid.com

1 page




NHI1599ET pdf
TABLE OF CONTENTS(continued)
8.2.1.9 ADDRESS FILTER (15:0)
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64
8.2.1.10 ADDRESS FILTER (31:16) . . . . . 64
8.2.2
MESSAGE MONITOR RAM .
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64
8.2.3
MESSAGE MONITOR MESSAGE TABLE .
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64
8.2.4
MESSAGE MONITOR TAG WORD .
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65
8.2.5
COMMAND WORD OR STATUS WORD
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65
8.2.6
DATA WORD( S)
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65
8.2.7
MESSAGE MONITOR EXAMPLE
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65
8.3.0
WORD MONITOR APPLICATIONS .
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65
8.3.1
WORD MONITOR REGISTERS
. . . . 66
8.3.1.1 CONFIGURATION REG 2 . . . . . 66
8.3.1.2 CONFIGURATION REG 1 . . . . . 66
8.3.1.3 BLOCK “A” START . . . . . . 66
8.3.1.4 BLOCK “A” END
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66
8.3.1.5 BLOCK “B” START . . . . . . 66
8.3.1.6 BLOCK “B” END
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66
8.3.1.7 CONDITION REGISTER . . . . . 66
8.3.1.8 WORD MONITOR END OF BLOCK OPTIONS . . . 67
8.3.1.9 CONFIGURATION REGISTER 3
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67
8.3.2
WORD MONITOR EXAMPLE .
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67
8.4.0
SIMULTANEOUS MONITOR AND REMOTE TERMINAL
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67
8.4.1
SIMULTANEOUS MODE INTERRUPT HANDLING .
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67
8.5.0
PC BOARD CONSIDERATIONS AND GUIDE LINES .
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68
9.0.0
PIN FUNCTIONAL DESCRIPTION .
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68
9.1.0
GENERAL PURPOSE SIGNALS
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69
9.2.0
HOST INTERFACE SIGNALS .
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69
9.3.0
DISCRETE I/ O BUS INTERFACE SIGNALS .
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70
9.4.0
MIL BUS INTERFACE SIGNALS
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71
10.0.0 ELECTRICAL CHARACTERISTICS . . . . 71
10.1.0
ABSOLUTE MAXIMUM RATINGS .
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71
10.2.0
OPERATING CONDITIONS .
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71
10.3.0
I/O TYPES & DESCRIPTIONS .
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72
10.4.0
I/O ELECTRICAL CHARACTERISTICS
. . . 72
11.0.0 TIMING DIAGRAMS . . . . . . 73
11.0.1
HOST WRITE CYCLE .
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73
11.0.2
HOST READ CYCLE .
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73
11.0.3
HOST READ- MODIFY- WRITE CYCLE
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74
11.0.4 RT HARDWARE INTERRUPT ACKNOWLEDGE CYCLE . 74
11.0.5
I/O WRITE CYCLE .
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75
11.0.6
I/O READ CYCLE
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75
11.0.7
COMMAND WRITE CYCLE .
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76
11.0.8
TERMINAL ADDRESS READ CYCLE .
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76
11.0.9
SOFTWARE INTERRUPT ACKNOWLEDGE CYCLE .
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77
11.0.10 TIMING DIAGRAM NOTES . . . . . 77
11.1.0
TIMING PARAMETER TABLES
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. 78
11.1.1
HOST READ, WRITE; READ- MODIFY- WRITE TABLE
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78
SOFTWARE INTERRUPT ACKNOWLEDGE
11.1.2
I/O READ and TERMINAL ADDRESS READ TABLE .
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78
11.1.3
I/O WRITE and COMMAND WRITE TABLE .
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78
11.1.4
HARDWARE INTERRUPT ACKNOWLEDGE TABLE .
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79
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5 Page





NHI1599ET arduino
3.3.0
PROTOCOL CHIP DESCRIPTION
The protocol chip contains the following modules:
Host Bus Interface Unit
I/ O Bus Interface Unit
Interrupt Controller Unit
Dual Redundant multi protocol Front End
Message Processor Unit
(HBIU)
(IBIU)
(ICU)
(DRFE)
(MPU)
3.3.1
HOST BUS INTERFACE UNIT
The HBIU provides a standard RAM interface to the host bus. The module performs the following
functions:
Provides NHi- ET device select and decodes host address to select registers.
Transfers data between the NHi-ET and the host (word and byte mode as well as read-
modify- write are supported).
Provides priority input and output for daisy chaining host interrupts.
Outputs *DTACK signal indicating end of bus cycle.
3.3.2
I/O BUS INTERFACE UNIT
The IBIU controls the RAM and I/ O residing on the I/ O bus so that it appears to the host as a
pseudo dual port RAM (i. e., shared memory). The unit implements the following functions:
Arbitrates between host and protocol chip initiated accesses to the RAM and host data
bus.
Decodes address lines to select device (e. g. RAM, external byte- wide I/ O, external
terminal address buffer, command output register).
Generates control signals to access the selected device.
3.3.3
INTERRUPT CONTROL UNIT
The ICU is an 8 input vectored interrupt controller. It contains eight registers as well as a FIFO for
storing pending interrupt vectors.
3.3.3.1 ICU REGISTERS
The ICU contains the following registers
INTERRUPT REQUEST register
INTERRUPT MASK register
INTERRUPT VECTOR register
AUXILIARY VECTOR register
(IRR)
(IMR)
(IVR)
(AVR)
The INTERRUPT REQUEST register samples 8 inputs originating from internal modules. Since
the host can write to this register, all interrupt sequences can be software driven for program
debugging. The inputs and their priorities (level 7 has highest priority) are described in the
following table.
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