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PDF DS2064 Data sheet ( Hoja de datos )
| Número de pieza | DS2064 | |
| Descripción | 8K x 8 Static RAM | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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DS2064
DS2064
8K x 8 Static RAM
FEATURES
• Low power CMOS design
• Standby current
50 nA max at tA = 25°C VCC = 3.0V
100 nA max at tA = 25°C VCC = 5.5V
1 µA max at tA = 60°C VCC = 5.5V
• Full operation for VCC = 4.5V to 5.5V
• Data Retention Voltage = 5.5V to 2.0V
• Access time equals 200 ns at 5.0V
• Operating temperature range of –40°C to +85°C
• Full static operation
• TTL compatible inputs and outputs
• Available in 28–pin DIP and 28–pin SOIC packages
• Suitable for both battery operated and battery backup
applications
PIN ASSIGNMENT
NC 1
A12 2
28 VCC
27 WE
A7 3
26 CE2
A6 4
25 A8
A5 5
24 A9
A4 6
23 A11
A3 7
22 OE
A2 8
21 A10
A1 9
20 CE1
A0 10
19 DQ7
DQ0 11
18 DQ6
DQ1 12
17 DQ5
DQ2 13
16 DQ4
GND 14
15 DQ3
DS2064–200 28–PIN DIP (600 MIL)
DS2064S–200 28–PIN SOIC (330 MIL)
PIN DESCRIPTION
A0–A12
DQ0–DQ7
CE1, CE2
WE
OE
VCC
GND
NC
– Address Inputs
– Data Input/Output
– Chip Enable Inputs
– Write Enable Input
– Output Enable Input
– 5V Power Supply Input
– Ground
– No Connection
DESCRIPTION
The DS2064 is a 65536–bit low power, fully static ran-
dom access memory organized as 8192 words by eight
bits using CMOS technology. The device operates from
a single power supply with a voltage input between 4.5V
and 5.5V. The chip enable inputs (CE1 and CE2) are
used for device selection and can be used in order to
achieve the minimum standby current mode, which fa-
cilitates both battery operate and battery backup appli-
cations. The device provides fast access time of 200 ns
and is most suitable for low power applications where
battery operation or battery backup for nonvolatility are
required. The DS2064 is a JEDEC–standard 8K x 8
SRAM and is pin–compatible with ROM and EPROM of
similar density.
022598 1/9
1 page  
TIMING DIAGRAM: WRITE CYCLE 2
ADDRESSES
CE
WE
VIH
VIL
tAW
VIH
tCOE
tWC
tWP
VIL VIL
VIL
tODW
VIL
VIH
VIL
tWR
VIH
VIH
VIH
VIL
DOUT
DIN
SEE NOTES 2, 3, 4, 5, 6 AND 7
tDS tDH
VIH
DATA IN STABLE
VIL
VIH
VIL
TIMING DIAGRAM: DATA RETENTION – POWER UP, POWER DOWN
VCC DATA RETENTION MODE
2.7V
CE
GND
SEE NOTE 8
tCDR
VIH
VCC - 0.2V
VIL
tR
DS2064
022598 5/9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet DS2064.PDF ] | |
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