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PDF KM6164000B Data sheet ( Hoja de datos )

Número de pieza KM6164000B
Descripción 256Kx16 bit Low Power CMOS Static RAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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KM6164000B Family
Document Title
256Kx16 bit Low Power CMOS Static RAM
Revision History
Revision No.
0.0
0.1
1.0
2.0
3.0
4.0
4.01
History
Initial draft
Revise
- Die name change ; A to B
Finalize
Revise
- Operating current update and release.
ICC(Read/Write) = 30/60 15/75mA
ICC1(Read/Write) = 30/60 15/75mA
ICC2 = 160 130mA
Revise
- Change datasheet format
- Remove ICC write value from table.
Revise
- Change test load at 55ns: 100pF 50pF
Errarta correction
CMOS SRAM
Draft Data
June 28, 1996
September 19, 1996
Remark
Advance
Preliminary
December 17, 1996
February 17, 1997
Final
Final
February 17, 1998
Final
June 22, 1998
August 8, 1998
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1 Revision 4.01
June 1998

1 page




KM6164000B pdf
KM6164000B Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :CL=100pF+1TTL
CL=50pF+1TTL
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS (Vcc=4.5~5.5V, Commercial product : TA=0 to 70°C, Industrial product : TA=-40 to 85°C)
Parameter List
Read
Write
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
UB, LB enable to low-Z output
Chip disable to high-Z output
OE disable to high-Z output
UB, LB disable to high-Z output
Output hold from address change
LB, UB valid to data output
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
LB, UB valid to end of write
Symbol
tRC
tAA
tCO
tOE
tLZ
tOLZ
tBLZ
tHZ
tOHZ
tBHZ
tOH
tBA
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
tBW
55ns
Min Max
55 -
- 55
- 55
- 25
10 -
5-
5-
0 20
0 20
0 20
10 -
- 25
55 -
45 -
0-
45 -
45 -
0-
0 20
25 -
0-
5-
45 -
Speed Bins
70ns
Min Max
70 -
- 70
- 70
- 35
10 -
5-
5-
0 25
0 25
0 25
10 -
- 35
70 -
60 -
0-
60 -
55 -
0-
0 25
30 -
0-
5-
60 -
100ns
Min Max
100 -
- 100
- 100
- 50
10 -
5-
5-
0 30
0 30
0 30
10 -
- 50
100 -
80 -
0-
80 -
70 -
0-
0 30
40 -
0-
5-
- 80
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
1. Industrial Product : 20µA
Symbol
VDR
IDR
tSDR
tRDR
Test Condition
CSVcc-0.2V
Vcc=3.0V
See data retention waveform
Min Typ Max Unit
2.0 - 5.5 V
- - 151) µA
0 - - ms
5- -
5 Revision 4.01
June 1998

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