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PDF IN24LC02B Data sheet ( Hoja de datos )
| Número de pieza | IN24LC02B | |
| Descripción | 2K 2.5V CMOS Serial EEPROMs | |
| Fabricantes | IK Semiconductor | |
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m TECHNICAL DATA
2K 2.5V CMeOt4SUS.ceorial EEPROMs IN24LC02B
taSheDESCRIPTION
aIN24LC02B is a 2K-bit Electrically Erasable PROM. The device is organized as a single
.Dblock of 256 x 8 bit memory with a two wire serial interface.
Low voltage design permits operation down to 2.5volts with standby and active currents
wof only 5µA and 1mA respectively.
wThe IN24LC02B also has a page-write capability for up to 8 bytes of data.
w The IN24LC02B is available in the standard 8-pin DIP.
FEATURES
m• Single supply with operation down to 2.5V
o• Low power CMOS technology
.c- 1 mA active current typical
- 10 µA standby current typical at 5.5V
U- 5 µA standby current typical at 3.0V
t4• Organized as a single block of 256 bytes (256x8)
e• Two wire serial interface bus, I2C compatible
e• Schmitt trigger, filtered inputs for noise suppression
• Output slope control to eliminate ground bounce
h• 100 kHz (2.5V) and 400 kHz (5V) compatibility
S• Self-timed write cycle (including auto-erase)
ta• Page-write buffer for up to 8 bytes
a• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
.D• Can be operated as a serial ROM
• Factory programming (QTP) available
w• ESD protection > 3,000V
w• 1,000,000 ERASE/WRITE cycles guaranteed*
w www.DataSheet4U.com• Data retention > 200 years
PACKAGE
TA = -40 ... +85 °C
PINNING
Name
Function
Vss Ground
SDA
Serial Address/Data I/O
SCL Serial Clock
WP Write Protect Input
VCC
+2.5V to 5.5V Power Supply
AO, A1, A2 No Internal Connection
Pin Connection
A0 1
A1 2
A2 3
Vss 4
8 Vcc
7 WP
6 SCL
5 SDA
1
1 page  
IN24LC02B
Note: The IN24LC02B does not generate any acknowledge bits if an internal programming cycle is in
progress
The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse
in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related
clock pulse. Of course, setup and hold times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked
out of the slave. In this case, the slave must leave the data line HIGH to enable the master to
generate the STOP condition.
Figure 4. Data Transfer Sequence on the serial bus
BUS CHARACTERISTICS
Slave Address
The IN24LC02B are software-compatible with devices such as 24C01A, 24C02A, 24LC01,
and 24LC02B. A single 24LC02B can be used in place of two 24LC01's,
for example, without any modifications to software.
The "chip select" portion of the control byte becomes a don't care.
After generating a START condition, the bus master transmits the slave address consisting
of a 4-bit device code (1010) for the IN24LC02B, followed by three don't care bits.
The eighth bit of slave address determines if the master device wants to read or write to
the IN24LC02B (see Figure 5).
The IN24LC0 monitors the bus for its corresponding slave address all the time.
It generates an acknowledge bit if the slave address was true and it is not in a programming
mode.
Operation
Read
Write
Control Code
1010
1010
Chip Select
XXX
XXX
R/W
1
0
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet IN24LC02B.PDF ] | |
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