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PDF TC58DVM82A1FT00 Data sheet ( Hoja de datos )
| Número de pieza | TC58DVM82A1FT00 | |
| Descripción | 256-MBIT (32M x 8 BITS) CMOS NAND E2PROM | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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TC58DVM82A1FT00
omTOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
U.c256-MBIT (32M × 8 BITS) CMOS NAND E2PROM
t4DESCRIPTION
eThe device is a 256-Mbit (276,824,064) bit NAND Electrically Erasable and Programmable Read-Only Memory
e(NAND E2PROM) organized as 528 bytes × 32 pages × 2048 blocks. The device uses single power supply (2.7 V to 3.6
hV for VCC). The device has a 528-byte static register which allows program and read data to be transferred between
Sthe register and the memory cell array in 528-byte increments. The Erase operation is implemented in a single block
taunit (16 Kbytes + 512 bytes: 528 bytes x 32 pages).
aThe device is a serial-type memory device which utilizes the I/O pins for both address and data input/output as
.Dwell as for command inputs. The Erase and Program operations are automatically executed making the device most
suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and
wother systems which require high-density non-volatile memory data storage.
wFEATURES
w • Organization
Memory cell allay 528 × 64K × 8
Register
528 × 8
Page size
528 bytes
mBlock size
(16K + 512) bytes
• Modes
oRead, Reset, Auto Page Program
.cAuto Block Erase, Status Read
• Mode control
Serial input/output
Command control
U• Power supply
t4Vcc: 2.7V to 3.6V
• Program/Erase Cycles 1E5 cycle (with ECC)
• Access time
eCell array to register 25 µs max
Serial Read Cycle 50 ns min
e• Operating current
Read (50 ns cycle) 10 mA typ.
hProgram (avg.)
10 mA typ.
Erase (avg.)
10 mA typ.
SStandby
50 µA max.
• Package
taTSOP I 48-P-1220-0.50 (Weight:0.53g typ)
aPIN ASSIGNMENT (TOP VIEW
.DNC
NC
NC
NC
wNC
GND
RY / BY
wRE
CE
NC
wNC
1
2
3
4
5
6
7
8
9
10
11
48
47
46
45
44
43
42
41
40
39
38
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
NC
NC
PINNAMES
I/O1 to I/O8
CE
WE
RE
CLE
I/O port
Chip enable
Write enable
Read enable
Command latch enable
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
12
13
14
15
16
17
18
19
20
21
22
23
24
37 VCC
36 VSS
35 NC
34 NC
33 NC
32 I/O4
31 I/O3
30 I/O2
29 I/O1
28 NC
27 NC
26 NC
25 NC
ALE
WP
RY/BY
GND
VCC
VSS
Address latch enable
mWrite protect
.coReady/Busy
UGround input
t4Power supply
eeGround
www.DataSh2003-03-25 1/34
1 page  
TC58DVM82A1FT00
Note: (1) CE High to Ready time depends on the pull-up resistor tied to the RY/BY pin.
(Refer to Application Note (9) toward the end of this document.)
(2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE to CE delay
is less than 30 ns, RY/BY signal stays Ready.
tCEH ≥ 100 ns
* *: VIH or VIL
CE
RE
525 526 527 A
A : 0 to 30 ns → Busy signal is not output.
RY/BY
Busy
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta =0° to 70°C, VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN TYP.
tPROG
Programming Time
N
Number of Programming Cycles on Same
Page
tBERASE
Block Erasing Time
(1): Refer to Application Note (12) toward the end of this document.
200
2
MAX
1000
3
10
UNIT
µs
ms
NOTES
(1)
2003-03-25 5/34
5 Page 
Sequential Read (1) Timing Diagram
CLE
TC58DVM82A1FT00
CE
WE
ALE
RE
00H
RY/BY
A0 toA7 A9 toA16 A17toA24
Column Page
address address
NM
tR
N N + 1 N + 2 527
012
tR
Page M
access
Page M + 1
access
: VIH or VIL
Sequential Read (2) Timing Diagram
527
CLE
CE
WE
ALE
RE
I/O1
to I/O8
01H
RY/BY
A0 toA7 A9 toA16 A17toA24
Column Page
address address
NM
tR
256 + 256 +
N N+1
Page M
access
527 0 1 2
tR
527
Page M + 1
access
: VIH or VIL
2003-03-25 11/34
11 Page | ||
| Páginas | Total 34 Páginas | |
| PDF Descargar | [ Datasheet TC58DVM82A1FT00.PDF ] | |
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