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PDF ICS2309 Data sheet ( Hoja de datos )

Número de pieza ICS2309
Descripción 3.3 VOLT ZERO DELAY / LOW SKEW BUFFER
Fabricantes Integrated Circuit Systems 
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ICS2309
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
Description
The ICS2309 is a low phase noise, high-speed PLL
based, low-skew zero delay buffer. Based on ICS’
proprietary low jitter Phase Locked Loop (PLL)
techniques, the device provides eight low skew outputs
at speeds up to 133 MHz at 3.3 V. The outputs can be
generated from the PLL (for zero delay), or directly
from the input (for testing), and can be set to tri-state
mode or to stop at a low level. The PLL feedback is
on-chip and is obtained from the CLKOUT pad.
The ICS2309 is available in two different versions. The
ICS2309-1 is the base part. The ICS2309-1H is a high
drive version with faster rise and fall times.
Block Diagram
VDD
2
Features
Clock outputs from 10 to 133 MHz
Zero input-output delay
Eight low skew (<250 ps) outputs
Device-to-device skew <700 ps
Full CMOS outputs with 25 mA output drive
capability at TTL levels
5 V tolerant CLKIN
Tri-state mode for board-level testing
Advanced, low power, sub-micron CMOS process
Operating voltage of 3.3 V
Industrial temperature range available
Packaged in 16-pin SOIC and TSSOP (-1H version
only)
Pb (lead) free package available for -1H version
(16-pin TSSOP only)
CLKIN
PLL
0
1
S2, S1 2
Control
Logic
GND 2
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
MDS 2309 D
1
Revision 052405
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

1 page




ICS2309 pdf
ICS2309
3.3 VOLT ZERO DELAY, LOW SKEW BUFFER
ICS2309M-1H, VDD=3.3 V ±10%, Ambient temperature -40 to +85°C(Industrial), (0-70°C Commercial),
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Output Clock Frequency
Output Clock Frequency
fIN 10 pF load, See table on page 2 10
30 pF load, See table on page 2 10
133 MHz
100 MHz
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
tOR 0.8 to 2.0 V, outputs loaded
tOF 2.0 to 0.8 V, outputs loaded
tDC measured at 1.4V, Fout=66.67 40
MHz
1.5
1.5
50 60
ns
ns
%
Output Clock Duty Cycle
tDC measured at 1.4V, Fout=50
MHz
45 50 55 %
Device to Device Skew
rising edges at VDD/2
700 ps
Output to Output Skew
rising edges at VDD/2
250 ps
Input to Output Skew
rising edges at VDD/2
±350 ps
Input to Output Skew
rising edges at VDD/2, S2= 1, 1 5 8.7 ns
S1 = 0
Cycle to Cycle Jitter
measured at 66.67M, outputs
loaded
200 ps
PLL Lock Time
Note 3
1.0 ms
Note 3: With VDD at a steady rate and valid input at CLKIN
MDS 2309 D
5
Revision 052405
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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