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PDF KM68V257C Data sheet ( Hoja de datos )

Número de pieza KM68V257C
Descripción 32K X 8 Bit High Speed CMOS Static RAM
Fabricantes Samsung Semiconductor 
Logotipo Samsung Semiconductor Logotipo



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No Preview Available ! KM68V257C Hoja de datos, Descripción, Manual

PRELIMINARY
KM68V257C .com CMOS SRAMDocument Title
t4U32Kx8 Bit High Speed Static RAM(3.3V Operating), Evolutionary Pin out.
heeRevision History
taSRevNo.
History
aRev. 0.0
Initial release with Preliminary.
w.DRev. 1.0
Release to final Data Sheet.
1. Delete Preliminary
ww Rev. 2.0
2.1. Add 28-TSOP1 Package.
omRev. 3.0
3.1. Delete DIP Package.
3.2. Delete 20ns part
3.3. Add Capacitive load of the test environment in A.C test load
Draft Data
Jun. 1st, 1994
Oct. 4th, 1994
Remark
Preliminary
Final
Feb. 22th, 1996
Feb. 25th, 1998
Final
Final
www.DataSheet4U.c taSheet4U.comThe attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
aspecifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
.Dtions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
www- 1 -
Rev 3.0
February 1998

1 page




KM68V257C pdf
KM68V257C
WRITE CYCLE
Parameter
Write Cycle Time
Chip Select to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
tWC
tCW
tAS
tAW
tWP
tWP1
tWR
tWHZ
tDW
tDH
tOW
KM68V257C-15
Min Max
15 -
11 -
0-
11 -
11 -
15 -
0-
06
8-
0-
0-
PRELIMINARY
CMOS SRAM
KM68V257C-17
Min Max
17 -
12 -
0-
12 -
12 -
17 -
0-
06
8-
0-
0-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
Address
Data Out
tOH
Previous Valid Data
tAA
tRC
Valid Data
-5-
Rev 3.0
February 1998

5 Page










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