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PDF S5L9274 Data sheet ( Hoja de datos )

Número de pieza S5L9274
Descripción DECODER FOR CD-MP3/CD-ROM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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No Preview Available ! S5L9274 Hoja de datos, Descripción, Manual

DECODER FOR CD-MP3/CD-ROM
S5L9274
INTRODUCTION
S5L9274 is a single chip ISO/IEC 11172-3 Layer III audio decoder, capable
of decoding compressed elementary bit stream as specified in ISO/IEC
standard. As a decoder for the DISC-MAN, it can provide you more small and
cheaper solution for MP3 player application.
S5L9274 is low voltage IC that can read MP3 and CD-ROM format discs and
can be applied to various products.
FEATURES
Single-chip ISO/IEC 11172-3 Layer III Audio Decoder
Support All MPEG Bit Rates including free format
Support 32/44.1/48 kHz Sampling Frequency for MPEG Bit Stream
Support Single Channel, Dual Channel, Stereo and Joint Stereo
Any Combination of Intensity Stereo & MS Stereo is supported
Serial Host Interface
Simple Software for Micom
Support Off-chip DAC interface
Anti Shock Memory Controller
Power Save Mode : POWER-DOWN, SLEEP (when paused)
Use of Standard Crystal 16.9344MHz
16.9344MHz Clock Output Port
Soft Mute Function
CDFS(CD-ROM File System) Decoding
Low Power Dissipation : 171mW @3.0 volts
ORDERING INFORMATION
64-LQFP-1010
Device
S5L9274X01-E0R0
Package
64-LQFP-1010
Supply Voltage
2.8V 3.3V
Operating Temperature
-20°C +75°C
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S5L9274 pdf
DECODER FOR CD-MP3/CD-ROM
PIN DESCRIPTION
Pin No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Symbol
VDD
XI
XO
XOUT
CLK
RESETB
PLL0 VDDA
PLL0 VSSA
PLL0 VBBA
FILTER_0
PLL1 VDDA
PLL1 VSSA
PLL1 VBBA
FILTER_1
PLL_BYPASS
VSS
VDD
ACLK EXT
CD CLK
CD DATA
CD LRCK
CD BCK
CD C2PO
ACLK
BCLK
LRCK
ADAT
EMP
ETYPE
N.C
N.C
VSS
I/O Description
P Digital Power
I X'tal Oscillator input(16.9344MHz)
O X'tal Oscillator output
O Buffered Output of XO
I System Clock input
I System Reset Active LOW
P Analog Power for PLL0
G Analog Ground for PLL0
G Analog Ground for PLL0
O External Capacitor port for PLL0
P Analog Power for PLL1
G Analog Ground for PLL1
G Analog Ground for PLL1
O External Capacitor port for PLL0
I Tied to GROUND.
G Digital Ground
P Digital Power
I External Audio Clock source
O Clock Output for CD DSP IC
I Data from CD DSP IC
I LRCK from CD DSP IC
I BCK from CD DSP IC
I C2PO from CD DSP IC
O Audio clock to DAC clock input
O BCLK to DAC
O LRCK to DAC
O Data to DAC
O Emphasis On/Off
O Indicates emphasis type
- No used
- No used
G Digital Ground
S5L9274
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S5L9274 arduino
DECODER FOR CD-MP3/CD-ROM
POWER MANAGEMENT
Power Save Modes
Down : Master Clock Disabled. Whole chip is in reset state and clocking is disabled.
(Host Interface ?, Clocks for CD-DSP chip ?)
Mode : All units suspended except hifUnit and DRAM Controller Block to refresh DRAM.
Running
S5L9274
Power Down
Sleep
System Power ON
Power down mode
Power down mode is implemented using MLAT, MCK, and MDAT. When the MLAT is low the MDAT is goes to
low, the CD-MP3 goes to "power down reset" mode. It means power ON state. When the MLAT is low and the
MCK goes to LOW, the CD-MP3 the "power down mode". The default value of MLAT, MCK, and MDAT is HIGH.
the system power becomes ON and the master reset comes, Micom should set the of MLAT, MCK, and MDAT to
HIGH. And should reset the power down mode of -MP3 using MLAT and MDAT LOW. Finally should send the
S/W reset to CD-MP3 H_SOFT_RST (8'hE0) register.
Sleep mode
In sleep mode, the minimal power is supplied which is needed just for DRAM refresh, host command, and etc.
There is a register H_SLEEP_CR to control Sleep . To enter sleep mode write "1xxxxxxx" into the
H_SLEEP_CR. To wake up from mode write "0xxxxxxx" into the H_SLEEP_CR.
_SLEEP_CR
8'hdf
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