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PDF DP8464B Data sheet ( Hoja de datos )

Número de pieza DP8464B
Descripción Disk Pulse Detector
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! DP8464B Hoja de datos, Descripción, Manual

June 1989
DP8464B Disk Pulse Detector
General Description
The DP8464B Disk Pulse Detector utilizes analog and digital
circuitry to detect amplitude peaks of the signal received
from the read write amplifier fitted with the heads of disk
drives The DP8464B produces a TTL compatible output
which on the positive leading edge indicates a signal peak
Electrically these peaks correspond to flux reversals on the
magnetic medium The signal from the read write amplifier
when reading a disk is therefore a series of pulses with
alternating polarity The Disk Pulse Detector accurately rep-
licates the time position of these peaks
The DP8464B Disk Pulse Detector has three main sections
the Amplifier the time channel and the gate channel The
Amplifier section consists of a wide bandwidth amplifier a
full wave rectifier and Automatic Gain Control (AGC) The
time channel is made from the differentiator and its follow-
ing bi-directional one shot while the gate channel is made
from the differential comparator with hysteresis the D flip-
flop and its following bi-directional one shot
The Disk Pulse Detector is fabricated using an advanced
oxide isolated Schottky process and has been designed to
function with data rates up to 15 Megabits second The
DP8464B is available in either a 300 mil wide 24-pin dual-in-
line package or a surface mount 28-pin plastic chip carrier
package Normally it will be fitted in the disk drive and its
output may be directly connected to the DP8461 or the
DP8465 Data Separator
Features
Y Wide input signal amplitude range from 20 mVpp to
660 mVpp differential
Y Data rates up to 15 Megabits sec 2 7 code
Y On-chip differential gain controlled amplifier differentia-
tor comparator gating circuitry and output pulse
generator
Y Input capacitively coupled directly from the disk head
read write amplifier
Y Adjustable comparator hysteresis
Y AGC and differentiator time constants set by external
components
Y TTL compatible digital Inputs and Outputs
Y Encoded Data Output may connect directly to the
DP8461 or DP8465 Data Separator
Y Standard drive supply 12Vg10%
Y Available in 300 mil wide 24-pin dual-in-line package a
surface mount 28-pin plastic chip carrier package or a
40-pin TapePak package
Block Diagram
Pin 5 No connection
Pin 8 No connection
Note All pin numbers in this data sheet refer to the 24-pin dual-in-line package
TapePak is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 5283
TL F 5283 – 7
RRD-B30M105 Printed in U S A

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DP8464B pdf
Circuit Operation (Continued)
of a differential comparator with hysteresis and a D flip-flop
The hysteresis for this comparator is externally set via the
Set Hysteresis pin In order to have data out the input am-
plitude must first cross the hysteresis level which will
change the logic level on the D input of the flip-flop The
peak of the input signal will generate a pulse out of the
differentiator and bi-directional one shot This pulse will
clock the new data at the D input through to the output In
this way when the differentiator is responding to noise at
the baseline the output of the D flop is not changing since
the logic level into the D input has not changed The com-
parator circuitry is therefore a gating channel which pre-
vents any noise near the baseline from contaminating the
data The amount of hysteresis is twice the DC voltage on
the Set Hysteresis pin For instance if the voltage on the
Set Hysteresis pin is 0 3V the differential AC signal across
the Gate Channel Input must be larger than 0 6V before the
output of the comparator will change states In this case
the hysteresis is 30% of a 2V peak to peak differential sig-
nal at the gate channel input
Connection Diagrams
Dual-In-Line (DIP) Package
Top View
Order Number DP8464BN-3 or DP8464BN-2
See NS Package N24C
Plastic Chip Carrier (PCC) Package
TL F 5283 – 2
TL F 5283 – 30
Order Number DP8464BV-3 DP8464BV-2 or DP8464BV-1
See NS Package V28A
5

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DP8464B arduino
Application Information (Continued)
AUTOMATIC GAIN CONTROL (AGC)
The Automatic Gain Control holds the signal level at the
Gate Channel Input at a constant level by controlling the
gain of the Gain Controlled Amplifier This is necessary be-
cause the amplitude of the input signal will vary with track
location variations in the magnetic film and differences in
the actual recording amplitude The Gain Controlled Amplifi-
er is designed for a maximum 4 Vpp differential output To
prevent the Gain Controlled Amplifier from saturating the
VREF level must be set so the maximum amplifier output
voltage is 4 Vpp The AGC will force the differential peak-to-
peak signal on the Gate Channel Input to be four times the
voltage applied to the VREF pin Normally some kind of filter
is connected between the Gain Controlled Amplifier’s output
and the Gate Channel Input Typically this filter has a 6 dB
insertion loss in its pass band Since the AGC holds the
amplitude at the Gate Channel Input constant this 6 dB loss
through the Gate Channel filter will cause the Gain Con-
trolled Amplifier’s output to be 6 dB larger than the Gate
Channel Input
The AGC loop starts out in the high gain mode When the
input signal is larger than expected the AGC loop will quick-
ly reduce the amplifier gain so the peak-to-peak differential
voltage on the Gate Channel Input remains four times the
voltage on VREF If the input amplitude suddenly drops the
AGC loop will slowly increase the amplifier gain until the
differential peak-to-peak Gate Channel Input voltage again
reaches four times VREF The AGC loop requires several
peaks to react to an increased input signal In order to re-
cover the exact peak timing during this transition the VOUT
level must be set somewhat lower than the maximum of
4 Vpp For instance if the VREF is 0 5V and if the loss in the
gate channel filter is 6 dB then the Amp Output is 4 Vpp If
the Amp Input suddenly increases 30% the amplifier may
saturate and the timing for a few peaks may be disturbed
until the AGC reduces the amplifier gain If the peak detec-
tion is critical during this time the system may fail The prop-
er operation for this example is to set the VREF at 0 35V so
the amplifier will not saturate if the input suddenly increases
30%
A simplified circuit of the AGC block is shown in Figure 6
When the full wave rectified signal from the Gate Channel
Input is greater than VREF the voltage on the collector of
transistor T1 will increase and charge up the external ca-
pacitor CAGC through T2 The typical available charging cur-
rent is 2 5 mA Conversely if this input is less than VREF
transistor T2 will be off so the capacitor CAGC will be dis-
charged by the base current going into the Darlington T3
and T4 This discharge current is approximately 1 mA The
voltage across CAGC controls the gain of the Gain Con-
trolled Amplifier This voltage will vary from typically 3 4V at
the highest gain to 4 5V at the lowest gain
When the AGC circuit has not received an input signal for a
long time the base current of the Darlington will discharge
the external CAGC to 3 4V The amplifier will now be at its
highest gain When a large signal comes in the external
CAGC will be charged up with the 2 4 mA from T2 thereby
reducing the gain of the amplifier The formula I e C c
(dV dt) can be used to calculate the time required for the
amplifier to go from a gain of 200 to a gain of 6 For in-
stance if CAGC e 0 01 mf the charging current I is 2 4 mA
and the dV required for the amplifier to go through its gain
range is 1 1V then
dt e (0 01 mF c 1 1V) (2 4 mA) or 4 6 ms
In reality the gain does not change this quickly since the
CAGC would only be charging during a portion of the input
waveform
By using the same argument the time required to increase
the amplifier gain after the input has been suddenly reduced
can be calculated This time the discharging current is only
1 ma so
dt e (0 01 mF c 1 1V) 1 mA) or 11 ms
FIGURE 6 Simplified AGC Circuit
11
TL F 5283 – 11

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