|
|
PDF DP8473 Data sheet ( Hoja de datos )
| Número de pieza | DP8473 | |
| Descripción | Floppy Disk Controller PLUS-2 | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DP8473 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
|
No Preview Available !
July 1990
DP8473 Floppy Disk Controller PLUS-2TM
General Description
This controller is a full featured floppy disk controller that is
software compatible with the mPD765A but also includes
many additional hardware and software enhancements
These enhancements include additional logic specifically re-
quired for an IBM PC PC-XT PC-AT or PS 2 design
This controller incorporates a precision analog data separa-
tor that includes a self trimming delay line and VCO Up to
three external filters are switched automatically depending
on the data rate selected This provides optimal perform-
ance at the standard PC data rates of 250 300 kb s and
500 kb s It also enables optimum performance at 1 Mb s
(MFM) These features combine to provide the lowest possi-
ble PLL bandwidth with the greatest lock range and hence
the widest window margin
This controller includes write precompensation circuitry A
shift register is used to provide a fixed 125 ns early-late
precompensation for all tracks at 500k 300k 250 kb s (83
ns for 1 MB s) or a precompensation value that scales with
(Continued)
Features
Y Fully mPD765A and IBM-BIOS compatible
Y Integrates all PCXT PCAT and most PS 2
On chip 24 MHz Crystal Oscillator
DMA enable logic
IBM compatible address decode of A0 – A2
12 mA mP bus interface buffers
48 mA floppy drive interface buffers
Data rate and drive control registers
Logic
Y Precision analog data separator
Self-calibrating PLL and delay line
Automatically chooses one of three filters
Intelligent read algorithm
Y Two pin programmable precompensation modes
Y Other enhancements
up to 1 Mb s data rate
Implied seek up to 4000 tracks
IBM or ISO formatting
Y Low power CMOS with power down mode
Connection Diagrams
Plastic Leaded Chip Carrier
Dual-In-Line Package
Top View
Order Number DP8473V
See NS Package Number V52A
TL F 9384 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
PLUS-2TM is a trademark of National Semiconductor Corporation
IBM PCXT PCAT and PS 2 are registered trademarks of International Business Machines Corporation
C1995 National Semiconductor Corporation TL F 9384
Top View
TL F 9384 – 2
Order Number DP8473N
See NS Package Number N48A
RRD-B30M105 Printed in U S A
1 page  
Typical Application
Recommended Plastic Chip Carrier Socket
AMP P N 821551-1 or equivalent
FIGURE 2 DP8473 Typical Application
TL F 9384 – 4
Functional Description
This section describes the basic architectural features of
the DP8473 and many of the enhancements provided Re-
fer to Figure 1
765A COMPATIBLE MICRO-ENGINE
The core of the DP8473 is a mPD765A compatible micro-
coded engine This engine consists of a sequencer pro-
gram ROM and disk misc registers This core is clocked by
either a 4 MHz 4 8 MHz or 8 MHz clock selected in the Data
Rate Register Upon this core is added all the glue logic
used to implement a PC-XT or AT or PS 2 floppy controller
as well as the data separator and write precompensation
logic
The controller consists of a microcoded engine that controls
the entire operation of the chip including coordination of
data transfer with the CPU controlling the drive controls
and actually performing the algorithms associated with
reading and writing data to from the disk This includes the
read algorithm for the data separator
Like the mPD765A this controller takes commands and re-
turns data and status through the Data Register in a byte
serial fashion Handshake for command status I O is pro-
vided via the Main Status Register All of the mPD765A
commands are supported as are many other enhanced
commands
DATA SEPARATOR
The internal data separator consists of an analog PLL and
its associated circuitry The PLL synchronizes the raw data
signal read from the disk drive The synchronized signal is
used to separate the encoded clock and data pulses The
data pulses are de-serialized into bytes and then sent to the
mP by the controller
The main PLL consists of four main components a phase
comparator a filter a voltage controlled oscillator (VCO)
and a programmable divider The phase comparator detects
the difference between the phase of the divider’s output and
the phase of the raw data being read from the disk This
phase difference is converted to a current which either
charges or discharges one of the three external filters The
resulting voltage on the filter changes the frequency of the
VCO and the divider output to reduce the phase difference
between the input data and the divider’s output The PLL is
‘‘locked’’ when the frequency of the divider is exactly the
same as the average frequency of the data read from the
disk A block diagram of the data separator is shown in Fig-
ure 3
5
5 Page 
Result Phase Status Registers (Continued)
D5 Seek End Seek or Recalibrate Command completed
by the Controller (Used during Sense Interrupt com-
mand )
D4 Equipment Check After a Recalibrate Command
Track 0 signal failed to occur (Used during Sense Inter-
rupt command )
D3 Not Used 0
D2 Head Address (at end of Execution Phase)
D1 D0 Drive Select (at end of Execution Phase)
00 e Drive 0 selected 01 e Drive 1 selected
10 e Drive 2 selected 11 e Drive 3 selected
STATUS REGISTER 1 (ST1)
D7 End of Track Controller transferred the last byte of the
last sector without the TC pin becoming active The last
sector is the End Of Track sector number programmed
in the Command Phase
D6 Not Used 0
D5 CRC Error If this bit is set and bit 5 of ST2 is clear
then there was a CRC error in the Address Field of the
correct sector If bit 5 of ST2 is set then there was a
CRC error in the Data Field
D4 Over Run Controller was not serviced by the mP soon
enough during a data transfer in the Execution Phase
TABLE VII Maximum Time Allowed to
Service an Interrupt or Acknowledge
a DMA Request in Execution Phase
Data
Rate
Time to
Service
125
250
500
1000
62 0 ms
30 0 ms
14 0 ms
6 0 ms
Time from rising edge of DRQ or INT to trailing edge of DAK or RD or WR
D3 Not Used 0
D2 No Data Three possible problems 1) Controller cannot
find the sector specified in the Command Phase during
the execution of a Read Write or Scan command An
address mark was found however so it is not a blank
disk 2) Controller cannot read any Address Fields with-
out a CRC error during Read ID command 3) Controller
cannot find starting sector during execution of Read A
Track command
D1 Not Writable Write Protect pin is active when a Write
or Format command is issued
D0 Missing Address Mark If bit 0 of ST2 is clear then the
disk controller cannot detect any Address Field Address
Mark after two disk revolutions If bit 0 of ST2 is set then
the disk controller cannot detect the Data Field Address
Mark
STATUS REGISTER 2 (ST2)
D7 Not Used 0
D6 Control Mark Controller tried to read a sector which
contained a deleted data address mark during execu-
tion of Read Data or Scan commands Or if a Read
Deleted Data command was executed a regular ad-
dress mark was detected
D5 CRC Error in Data Field Controller detected a CRC
error in the Data Field Bit 5 of ST1 is also set
D4 Wrong Track Only set if desired sector not found and
the track number recorded on any sector of the current
track is different from that stored in the Track Register
D3 Scan Equal Hit ‘‘Equal’’ condition satisfied during any
Scan Command
D2 Scan Not Satisfied Controller cannot find a sector on
the track which meets the desired condition during Scan
Command
D1 Bad Track Only set if the desired sector is not found
and the track number recorded on any sector on the
track is different from that stored in the Track Register
and the recorded track number is FF
D0 Missing Address Mark in Data Field Controller can-
not find the Data Field Address Mark during Read Scan
command Bit 0 of ST1 is also set
STATUS REGISTER 3 (ST3)
D7 Not Used 0
D6 Write Protect Status
D5 Not Used 1
D4 Track 0 Status
D3 Not Used 0
D2 Head Select Status
D1 D0 Drive Selected
00 e Drive 0 selected 01 e Drive 1 selected
10 e Drive 2 selected 11 e Drive 3 selected
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet DP8473.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DP8470 | Floppy Disk Support Chip Data Separator & Write Precompensation | National Semiconductor |
| DP8473 | Floppy Disk Controller PLUS-2 | National Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |