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PDF DP84910 Data sheet ( Hoja de datos )
| Número de pieza | DP84910 | |
| Descripción | Integrated Read Channel | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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October 1994
DP84910 (-36 -50)
Integrated Read Channel
General Description
The DP84910 integrates most functions of the hard disk
read channel electronics onto a single 5V chip It incorpo-
rates a pulse servo detector a programmable integrated
channel filter a data synchronizer a frequency synthesizer
and a serial port interface The chip receives data from a
read preamplifier filters and peak detects the read pulses
for both data and embedded servo information and resyn-
chronizes the data with the system clock
The DP84910 is available in two versions DP84910VHG-36
and DP84910VHG-50 The DP84910VHG-36 is specified to
operate over a data rate range of 7 5 Mbits sec to
36 Mbits sec The other version DP84910VHG-50 will op-
erate over a data rate range of 13 7 Mbits sec to 50 Mbits
sec
This device is specifically designed to address zoned data
rate applications A channel filter with control register se-
lectable cutoff frequency and equalization is provided on-
chip This eliminates the need for multiple external channel
filters and allows for greater flexibility in the selection of
zone frequencies The frequency synthesizer provides cen-
ter frequency information for the data synchronizer and a
variable frequency write clock There is no need for any off-
chip frequency setting components or DACs
A four-bank control register is included to control zoning
operations and configure general chip functions At VCC
power-up the chip self-configures by presetting all bits in the
control register to predetermined operating setup condi-
tions
Independent power down control for all of the major blocks
within the chip is provided via three bits in the control
register (SYNC PWR DN STH PWR DN and
PD PWR DN) to manage power consumption In addi-
tion two pins (SLEEP and IDLE SERVO) are available to
control power management The sleep mode pin (SLEEP)
powers down all circuitry on the chip including the control
register In this mode the maximum power supply current is
2 mA the control register data must be reentered when
exiting this mode The idle servo mode pin (IDLE SERVO)
toggles the device between the idle and servo modes In the
idle mode only the control register and pulse detector bias-
ing circuitry necessary for a quick recovery are active In the
servo mode the pulse detector portions needed for servo
detection are active as well as the control register Less
than 15 ms is required for the pulse detector to recover from
the idle condition The control register data is not lost when
this pin is toggled The pin can be rapidly toggled (k15 ms)
to achieve average power consumption savings and will
keep the read write head on track Seventeen power and
ground pins are provided to isolate major functional blocks
and allow for independent supply voltage filtering thus en-
hancing noise immunity
(Continued)
FIGURE 1 DP84910 in a Typical Disk Drive System
TL F 11777 – 1
MICROWIRETM is a trademark of National Semiconductor Corporation
C1996 National Semiconductor Corporation TL F 11777
RRD-B30M116 Printed in U S A
http www national com
1 page  
Pin Definitions (Continued)
Pin Description
POWER SUPPLY AND GROUND PINS (Continued)
65 PULSE DETECTOR ANALOG SUPPLY VOLTAGE (PAVCC) 5V a5 b10%
66 PULSE DETECTOR ANALOG GROUND (PAGND)
68 FILTER ANALOG SUPPLY VOLTAGE (FVCC) 5V a5 b10%
69 FILTER ANALOG GROUND (FGND)
72 SYNCHRONIZER PLL ANALOG SUPPLY VOLTAGE (SYCVCC) 5V a5 b10%
75 SYNCHRONIZER PLL ANALOG GROUND (SYCGND)
78 SYNTHESIZER PLL ANALOG SUPPLY VOLTAGE (STHVCC) 5V a5 b10%
80 SYNTHESIZER PLL ANALOG GROUND (STHGND)
TTL LEVEL LOGIC PINS
1 WRITE GATE INPUT (WG) This pin receives the write mode control input signal from the controller The logic polarity
for WG assertion is selectable via a bit in the control register (INV WG Bank (1 1) bit 5) WG is active low if the control
register bit is set to invert (INV WG e 1) When WG is active the pulse detector inputs (AMPIN1 and AMPIN2) are
held in a low impedance state and the automatic gain control of the puIse detector is in the hold mode There are no
setup or hold timing restrictions on WG enabling or disabling
2 IDLE SERVO BAR POWER DOWN INPUT (IDLE SERVO) This input controls the power status of the servo detection
circuitry in the pulse detector When high (idle mode) this pin powers down all pulse detector circuitry except for biasing
circuitry necessary for quick recovery (k 15 ms) from this mode When low (servo mode) this pin powers on the circuitry
necessary for servo information detection in the puIse detector The synchronizer and synthesizer power are unaffected
by this pin The controI register power is also unaffected by the IDLE SERVO pin but its input buffers are The control
register’s input’s are only powered on when the IDLE SERVO pin is low Thus the controI register cannot be loaded
when the IDLE SERVO pin is high The contents of the controI register is not affected by the state of the IDLE SERVO
pin
3 SLEEP BAR POWER DOWN INPUT (SLEEP) This active low input powers down aIl circuitry on the chip The control
register is powered down in this mode thus it does not retain its information The control register wiII be reset to the
initial power-on conditions when exiting the sleep mode The maximum supply current in the sleep mode is 2 mA
4 CONTROL REGISTER LATCH SHIFT BAR INPUT (CRL S) A logical low on this input allows the CONTROL
REGISTER CLOCK input to shift data into the control register’s shift register via the CONTROL REGISTER DATA input
A positive transition latches the data into the addressed bank of latches and issues the information to the appropriate
circuitry within the device To minimize power consumption this pin should be kept at a logical high state except when
shifting data into the control register The SLEEP and IDLE SERVO pins must be disabled (SLEEP e high and
IDLE SERVO e low) in order to shift data into the control register
5 CONTROL REGISTER DATA INPUT (CRD) ControI register data input
6 CONTROL REGISTER CLOCK INPUT (CRC) Positive-edge-active control register clock input
7 FREQUENCY LOCK CONTROL BAR INPUT (FLC) This input enables or disables the frequency lock function during a
read operation It has no effect when READ GATE is disabled Frequency lock is automatically employed for the full
duration of the time READ GATE is disabled regardless of the level of this input When READ GATE is taken to a logical
high level while FLC is at a logical low level (frequency lock enabled) the PLL is forced to lock to the pattern frequency
(2T or 3T sync field) selected in the control register (PREAM 2T Bank (1 1) bit 4) When FLC is taken to a logical high
level the frequency lock action is terminated and the PLL employs a pulse gate to accommodate random disk data
patterns There are no setup or hold timing restrictions on the positive-going transition of FLC
8 PREAMBLE DETECTED OUTPUT (PDT) This output issues a logical high state after the following sequence the
enabling of READ GATE the completion of the zero-phase-start sequence and the detection of approximately 16
sequential pulses of 2T or 3T preamble Following preamble detection this output remains latched high until READ
GATE is disabled This output will be at a logical low state whenever READ GATE is inactive (low)
9 READ GATE INPUT (RG) This input receives the read mode control input signal from the controller active high for a
read operation There are no setup or hold timing restrictions on RG enabling or disabling
10 DELAY LINE OUTPUT (DLO) This active low open collector output pin issues encoded read data (ERD) delayed by
the selected value in the delay line at the input to the synchronizing latch By viewing this signal’s phase the user can
directly view the amount of window movement as the control register’s strobe bits are changed
5 http www national com
5 Page 
DC Electrical Characteristics General guaranteed over operating conditions (see table) unless oth-
erwise specified Minimum and or maximum limits are guaranteed by outgoing testing unless otherwise specified
Symbol
Parameter
Conditions
Min
VIC
VOH
Input Clamp Voltage
High Logic Level
Output Voltage
VCC e Min II e b18 mA
VCC e Min IOH e Max
b0 65
VCC b 2
VOL
Low Logic Level
VCC e Min IOL e Max
Output Voltage
IIH
High Logic Level
VCC e Max VI e 2 7V
Input Current
IIL
Low Logic Level
VCC e Max VI e 0 4V
Input Current
IO
ICPO
Output Drive Current
Charge Pump Output
Current
VCC e Max VO e 2 125V (Note 1)
(Note 2)
b12
0 8 K1IIN
IDRIFT
Combined Charge
Pump Output
Inactive Current and
VCOI OFFSET
Current
Charge Pump Inactive CPO and VCOI
pins tied together
1V k VCPO k 2 5V
b1 2
ITEF TEF Output Current 1V k VTEF k 2 5V
(Absolute Value)
250
ITEF-OFF
TEF Output Inactive
Current
1V k VTEF k 2 5V
b1
VRNOM
VCPO(PD)
Voltage at RNOM Pin
CPO Voltage with
Synchronizer
Powered Down
IRNOM e 125 mA 25 C only
b5 mA k ICPO k 5 mA
06
11
VTEF(PD)
TEF Voltage with
Synthesizer Powered
Down
b5 mA k ITEF k 5 mA
11
ICCR
Supply Current in the
Read Mode
V(WG) e 0 3V All Sections 16 7 Mb s
Powered On VCC e 5 25V 33 3 Mb s
50 Mb s
ICC(SLEEP) Supply Current in
Sleep Mode
V(SLEEP) e 0 8V VCC e 5 25V
ICC(IDLE)
ICC(PD)
Supply Current in Idle
Mode
Pulse Detector
Supply Current with
All Other Sections
Powered Down
V(WG) e 0 3V Power Down
Synchronizer and Synthesizer Sections
of the Chip Via Control Register Power
Down Pulse Detector with IDLE Pin
VCC e 5 25V
V(WG) e 0 3V Power Down All Sections
of the Chip Via Control Register Except
the Pulse Detector VCC e 5 25V
VSVCC
Switched Supply
(SVCC) Output
Voltage
SLEEP e HIGH Pull 1 mA from SVCC
pin
VCC b 1 1
Note 1 VO e 2 125V produces a current closely approximating one half of the true short circuit current IOS
Note 2 K1 is the selected charge pump gain constant (2 4 or 8) IIN e IRNOM 1V k VCPO k 2 5V
Note 3 Typical values are specified at 25 C and 5V supply
Typ
(Note 3)
1
VCC b 1 6
0 25
1
b60
K1IIN
0 75
15
15
160
175
200
1
10
VCC b 1
Max
b1 5
05
20
b200
b110
1 2 K1IIN
12
800
1
09
2
2
190
200
220
25
20
110
VCC b 0 9
Units
V
V
V
mA
mA
mA
mA
mA
mA
V
V
V
mA
mA
mA
mA
mA
mA
V
11 http www national com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DP84910.PDF ] | |
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