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PDF DP8422V Data sheet ( Hoja de datos )
| Número de pieza | DP8422V | |
| Descripción | microCMOS Programmable 256k/1M/4M Dynamic RAM Controller/Drivers | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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May 1992
DP8420V 21V 22V-33 DP84T22-25 microCMOS
Programmable 256k 1M 4M Dynamic RAM
Controller Drivers
General Description
The DP8420V 21V 22V-33 DP84T22-25 dynamic RAM
controllers provide a low cost single chip interface between
dynamic RAM and all 8- 16- and 32-bit systems The
DP8420V 21V 22V-33 DP84T22-25 generate all the re-
quired access control signal timing for DRAMs An on-chip
refresh request clock is used to automatically refresh the
DRAM array Refreshes and accesses are arbitrated on
chip If necessary a WAIT or DTACK output inserts wait
states into system access cycles including burst mode ac-
cesses RAS low time during refreshes and RAS precharge
time after refreshes and back to back accesses are guaran-
teed through the insertion of wait states Separate on-chip
precharge counters for each RAS output can be used for
memory interleaving to avoid delayed back to back access-
es because of precharge An additional feature of the
DP8422V DP84T22 is two access ports to simplify dual ac-
cessing Arbitration among these ports and refresh is done
on chip To make board level circuit testing easier the
DP84T22 incorporates TRI-STATE output buffers
Features
Y On chip high precision delay line to guarantee critical
DRAM access timing parameters
Y microCMOS process for low power
Y High capacitance drivers for RAS CAS WE and DRAM
address on chip
Y On chip support for nibble page and static column
DRAMs
Y TRI-STATE outputs (DP84T22 only)
Y Byte enable signals on chip allow byte writing in a word
size up to 32 bits with no external logic
Y Selection of controller speeds 25 MHz and 33 MHz
Y On board Port A Port B (DP8422V DP84T22 only) re-
fresh arbitration logic
Y Direct interface to all major microprocessors (applica-
tion notes available)
Y 4 RAS and 4 CAS drivers (the RAS and CAS configura-
tion is programmable)
Control
DP8420V
DP8421V
DP8422V
DP84T22
of Pins
(PLCC)
68
68
84
84
of Address
Outputs
9
10
11
11
Largest
DRAM
Possible
256 kbit
1 Mbit
4 Mbit
4 Mbit
Direct Drive
Memory
Capacity
4 Mbytes
16 Mbytes
64 Mbytes
64 Mbytes
Access
Ports
Available
Single Access Port
Single Access Port
Dual Access Ports (A and B)
Dual Access and TRI-STATE
Block Diagram
DP8420V 21V 22V DP74T22 DRAM Controller
TRI-STATE is a registered trademark of National Semiconductor Corporation
Staggered RefreshTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11109
FIGURE 1
TL F 11109 – 1
RRD-B30M105 Printed in U S A
1 page  
2 0 Signal Descriptions
Pin
Name
Device (If Not Input
Applicable to All) Output
Description
2 1 ADDRESS R W AND PROGRAMMING SIGNALS
R0 – 10
R0 – 9
DP8422V T22
DP8420V 21V
I ROW ADDRESS These inputs are used to specify the row address during an access
I to the DRAM They are also used to program the chip when ML is asserted (except
R10)
C0 – 10
C0 – 9
DP8422V T22
DP8420V 21V
I COLUMN ADDRESS These inputs are used to specify the column address during an
I access to the DRAM They are also used to program the chip when ML is asserted
(except C10)
B0 B1
I BANK SELECT Depending on programming these inputs are used to select a group
of RAS and CAS outputs to assert during an access They are also used to program
the chip when ML is asserted
ECAS0 – 3
I ENABLE CAS These inputs are used to enable a single or group of CAS outputs
when asserted In combination with the B0 B1 and the programming bits these
inputs select which CAS output or CAS outputs will assert during an access The
ECAS signals can also be used to toggle a group of CAS outputs for page nibble
mode accesses They also can be used for byte write operations If ECAS0 is
negated during programming continuing to assert the ECAS0 while negating AREQ
or AREQB during an access will cause the CAS outputs to be extended while the
RAS outputs are negated (the ECASn inputs have no effect during scrubbing
refreshes)
WIN
I WRITE ENABLE IN This input is used to signify a write operation to the DRAM If
ECAS0 is asserted during programming the WE output will follow this input This
input asserted will also cause CAS to delay to the next positive clock edge if address
bit C9 is asserted during programming
COLINC
(EXTNDRF)
I COLUMN INCREMENT When the address latches are used and RFIP is negated
I this input functions as COLINC Asserting this signal causes the column address to
be incremented by one When RFIP is asserted this signal is used to extend the
refresh cycle by any number of periods of CLK until it is negated
ML I MODE LOAD This input signal when low enables the internal programming register
that stores the programming information
2 2 DRAM CONTROL SIGNALS
Q0 – 10
Q0 – 9
Q0 – 8
DP8422V T22
DP8421V
DP8421V
O DRAM ADDRESS These outputs are the multiplexed output of the R0 – 9 10 and
O C0–9 10 and form the DRAM address bus These outputs contain the refresh
O address whenever RFIP is asserted They contain high capacitive drivers with 20X
series damping resistors
RAS0 – 3
O ROW ADDRESS STROBES These outputs are asserted to latch the row address
contained on the outputs Q0 – 8 9 10 into the DRAM When RFIP is asserted the
RAS outputs are used to latch the refresh row address contained on the Q0 – 8 9 10
outputs in the DRAM These outputs contain high capacitive drivers with 20X series
damping resistors
CAS0 – 3
O COLUMN ADDRESS STROBES These outputs are asserted to latch the column
address contained on the outputs Q0 – 8 9 10 into the DRAM These outputs have
high capacitive drivers with 20X series damping resistors
WE
(RFRQ)
O WRITE ENABLE or REFRESH REQUEST This output asserted specifies a write
O operation to the DRAM When negated this output specifies a read operation to the
DRAM When the controller is programmed in address pipelining mode or when
ECAS0 is negated during programming this output will function as RFRQ When
asserted this pin specifies that 13 ms or 15 ms have passed If DISRFSH is negated
the DP8420V 21V 22V DP84T22 will perform an internal refresh as soon as
possible If DISRFRSH is asserted RFRQ can be used to externally request a refresh
through the input RFSH This output has a high capacitive driver and a 20X series
damping resistor
OE DP84T22
(Only)
I OUTPUT ENABLE This input asserted enables the output buffers for the row
column RASs CASs and WE If this input is disabled logic 1 the output buffers are at
TRI-STATE facilitating the board level circuit testing
5
5 Page 
3 0 Programming and Resetting (Continued)
3 3 PROGRAMMING BIT DEFINITIONS (Continued)
Symbol
C6 C5 C4
101
110
111
C3
0
1
C2 C1 C0
000
001
010
011
100
101
110
111
R9
0
1
R8
0
1
R7
0
1
R6
0
1
Description
RAS and CAS Configuration Modes (Continued)
RAS and CAS pairs are selected by B1 ECASn must be asserted for CASn to be asserted
B1 e 0 during an access selects RAS0 – 1 and CAS0 – 1
B1 e 1 during an access selects RAS2 – 3 and CAS2 – 3
B0 is not used during an access
No error scrubbing
RAS singles are selected by B0–1 CAS0 – 3 are all selected ECASn must be asserted for CASn to be
asserted
B1 e 0 B0 e 0 during an access selects RAS0 and CAS0 – 3
B1 e 0 B0 e 1 during an access selects RAS1 and CAS0 – 3
B1 e 1 B0 e 0 during an access selects RAS2 and CAS0 – 3
B1 e 1 B0 e 1 during an access selects RAS3 and CAS0 – 3
No error scrubbing
RAS and CAS singles are selected by B0 1 ECASn must be asserted for CASn to be asserted
B1 e 0 B0 e 0 during an access selects RAS0 and CAS0
B1 e 0 B0 e 1 during an access selects RAS1 and CAS1
B1 e 1 B0 e 0 during an access selects RAS2 and CAS2
B1 e 1 B0 e 1 during an access selects RAS3 and CAS3
No error scrubbing
Refresh Clock Fine Tune Divisor
Divide delay line refresh clock further by 30 (If DELCLK Refresh Clock Clock Divisor e 2 MHz e 15 ms
refresh period)
Divide delay line refresh clock further by 26 (If DELCLK Refresh Clock Clock Divisor e 2 MHz e 13 ms
refresh period)
Delay Line Refresh Clock Divisor Select
Divide DELCLK by 10 to get as close to 2 MHz as possible
Divide DELCLK by 9 to get as close to 2 MHz as possible
Divide DELCLK by 8 to get as close to 2 MHz as possible
Divide DELCLK by 7 to get as close to 2 MHz as possible
Divide DELCLK by 6 to get as close to 2 MHz as possible
Divide DELCLK by 5 to get as close to 2 MHz as possible
Divide DELCLK by 4 to get as close to 2 MHz as possible
Divide DELCLK by 3 to get as close to 2 MHz as possible
Refresh Mode Select
RAS0–3 will all assert and negate at the same time during a refresh
Staggered Refresh RAS outputs during refresh are separated by one positive clock edge Depending on the
configuration mode chosen either one or two RASs will be asserted
Address Pipelining Select
Address pipelining is selected The DRAM controller will switch the DRAM column address back to the row
address after guaranteeing the column address hold time
Non-address pipelining is selected The DRAM controller will hold the column address on the DRAM address
bus until the access RASs are negated
WAIT or DTACK Select
WAIT type output is selected
DTACK (Data Transfer ACKnowledge) type output is selected
Add Wait States to the Current Access if WAITIN is Low
WAIT or DTACK will be delayed by one additional positive edge of CLK
WAIT or DTACK will be delayed by two additional positive edges of CLK
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DP8422V.PDF ] | |
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