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PDF PC7410 Data sheet ( Hoja de datos )
| Número de pieza | PC7410 | |
| Descripción | PowerPC 7410 RISC Microprocessor | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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PC7410
PowerPC 7410 RISC Microprocessor
Datasheet
Features
• 22.8 SPECint95 (estimated), 17SPECfp95 at 500 MHz (estimated)
• 917MIPS at 500 MHz
• Selectable Bus Clock (14 CPU Bus Dividers Up To 9x)
• Seven Selectable Core-to-L2 Frequency Divisors
• Selectable 603 Interface Voltage Below 3.3V (1.8V, 2.5V)
• Selectable L2 interface of 1.8V or 2.5V
• PD Typical 5.3W at 500 MHz, Full Operating Conditions
• Nap, Doze and Sleep Modes for Power Saving
• Superscalar (Four Instructions fetched per Clock Cycle)
• 4 GB Direct Addressing Range
• Virtual Memory: 4 hexabytes (252)
• 64-bit Data and 32-bit Address Bus Interface
• 32 KB Instruction and Data Cache
• Eight Independent Execution Units and Three Register Files
• Write-back and Write-through Operations
• fINT Max = 450 MHz 500 MHz
• fBUS Max = 133 MHz
Description
The PC7410 is the second microprocessor that uses the fourth (G4) full implementation of the PowerPC Reduced Instruc-
tion Set Computer (RISC) architecture. It is fully JTAG-compliant.
The PC7410 maintains some of the characteristics of G3 microprocessors:
• The design is superscalar, capable of issuing three instructions per clock cycle into eight independent execution units
• The microprocessor provides four software controllable power-saving modes and a thermal assist unit management
• The microprocessor has separate 32-Kbyte, physically-addressed instruction and data caches with dedicated L2 cache
interface with on-chip L2 tags
In addition, the PC7410 integrates full hardware-based multiprocessing capability, including a 5-state cache coherency pro-
tocol (4 MESI states plus a fifth state for shared intervention) and an implementation of the new AltiVec® technology
instruction set.
New features have been developed to make latency equal for double-precision and single-precision floating-point opera-
tions involving multiplication. Additionally, in memory subsystem (MSS) bandwidth, the PC7410 offers an optional, high-
bandwidth MPX bus interface.
Unlike the PC7400, the PC7410 does not support the 3.3V I/O on the L2 cache interface.
e2v semiconductors SAS 2007
Visit our website: www.e2v.com
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PC7410
• Completion
– 8-entry completion buffer
– Instruction tracking and peak completion of two instructions per cycle
– Completion of instructions in program order while supporting out-of-order instruction
execution, completion serialization and all instruction flow changes
• Fixed-point Units (FXUs) that Share 32 GPRs for Integer Operands
– Fixed-point Unit 1 (FXU1): multiply, divide, shift, rotate, arithmetic, logical
– Fixed-point Unit 2 (FXU2)—shift, rotate, arithmetic, logical
– Single-cycle arithmetic, shifts, rotates, logical
– Multiply and divide support (multi-cycle)
– Early out multiply
• Three-stage Floating-point Unit and a 32-entry FPR File
– Support for IEEE-754 standard single- and double-precision floating-point arithmetic
– Three-cycle latency, one-cycle throughput (single or double precision)
– Hardware support for divide
– Hardware support for denormalized numbers
– Time deterministic non-IEEE mode
• System Unit
– Executes CR logical instructions and miscellaneous system instructions
– Special register transfer instructions
• AltiVec Unit
– Full 128-bit data paths
– Two dispatchable units: vector permute unit and vector ALU unit
– Contains its own 32-entry 128-bit Vector Register File (VRF) with six renames
– The vector ALU unit is further sub-divided into the Vector Simple Integer Unit (VSIU), the
Vector Complex Integer Unit (VCIU) and the Vector Floating-point Unit (VFPU)
– Fully pipelined
• Load/Store Unit
– One-cycle load or store cache access (byte, half-word, word, double-word)
– Two-cycle load latency with one-cycle throughput
– Effective address generation
– Hits under misses (multiple outstanding misses)
– Single-cycle unaligned access within double-word boundary
– Alignment, zero padding, sign extend for integer register file
– Floating-point internal format conversion (alignment, normalization)
– Sequencing for load/store multiples and string operations
– Store gathering
– Executes the cache and TLB instructions
– Big- and little-endian byte addressing supported
– Misaligned little-endian supported
e2v semiconductors SAS 2007
0832F–HIREL–02/07
5
5 Page 
PC7410
6.3 Recommended Operating Conditions
Table 6-3. Recommended Operating Conditions(1)
Symbol
Characteristic
Recommended
Value
Unit
VDD Core supply voltage
1.8 ± 100 mV
or 1.5 ± 50 mV
V
AVDD
PLL supply voltage
1.8 ± 100 mV
or 1.5 ± 50 mV
V
L2AVDD
L2 DLL supply voltage
1.8 ± 100 mV
or 1.5 ± 50 mV
V
OVDD
OVDD
OVDD(2)(3)
Processor bus supply voltage see note (3)
BVSEL = 0
BVSEL = HRESET
BVSEL = 1 or = HRESET(4)
1.8 ± 100 mV
2.5 ± 100 mV
3.3 ± 165 mV
V
V
V
L2OVDD
L2OVDD
L2 bus supply voltage
L2VSEL = 0
L2VSEL = 1(2) or L2VSEL = HRESET
1.8 ± 100 mV
2.5 ± 100 mV
V
V
VIN
Processor bus
GND to OVDD
V
VIN Input voltage
L2 Bus
GND to L2OVDD
V
VIN
JTAG Signals
GND to OVDD
V
TJ Die-junction temperature
-55 to 125
°C
Notes: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not
guaranteed.
2. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3V OVDD and have a recommended OVDD
value of 2.5V ±100 mV for BVSEL = 1.
3. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support BVSEL = HRESET.
4. Not supported for N spec with VDD = 1.5V
e2v semiconductors SAS 2007
0832F–HIREL–02/07
11
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| PDF Descargar | [ Datasheet PC7410.PDF ] | |
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