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PDF M37517F8HP Data sheet ( Hoja de datos )
| Número de pieza | M37517F8HP | |
| Descripción | Single-Chip 8-Bit CMOS Microcomputer | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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7517 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0087-0101Z
Rev.1.01
Aug 02, 2004
DESCRIPTION
The 7517 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 7517 group is designed for battery-pack and includes serial
interface functions, 8-bit timer, A/D converter, current integrator
and I2C-BUS interface.
FEATURES
qBasic machine-language instructions ...................................... 71
qMinimum instruction execution time .................................. 1.0 µs
(at 4 MHz oscillation frequency)
qMemory size
Flash memory ............................................................... 32 kbytes
RAM ................................................................................ 1 kbytes
qProgrammable input/output ports ............................................ 36
qInterrupts ................................................. 19 sources, 16 vectors
qTimers ............................................................................. 8-bit ✕ 4
qSerial I/O1 ................... 8-bit ✕ 1 (UART or Clock-synchronized)
qSerial I/O2 ................................... 8-bit ✕ 1(Clock-synchronized)
qMulti-master I2C-BUS interface (option) ...................... 1 channel
qPWM ............................................................................... 8-bit ✕ 1
qA/D converter ............................................. 10-bit ✕ 10 channels
q Current integrator ......................................................... 1 channel
q Over current detector ................................................... 1 channel
q Watchdog timer ............................................................ 16-bit ✕ 1
q Clock generating circuit ..................................... Built-in 4 circuits
(built-in 4MHz on-chip oscillator and 32kHz RC oscillator, or con-
nect to external ceramic resonator or quartz-crystal oscillator)
qPower source voltage
In high-speed mode .................................................. 3.0 to 3.6 V
(at 4 MHz oscillation frequency)
In middle-speed mode ............................................... 3.0 to 3.6 V
(at 8 MHz oscillation frequency)
In low-speed mode .................................................... 3.0 to 3.6 V
(at 32 kHz oscillation frequency)
qPower dissipation
In high-speed mode ...................................................... 8.25 mW
(at 4 MHz oscillation frequency, at 3.3 V power source voltage)
In low-speed mode ........................................................... 660µW
(at 32 kHz oscillation frequency, at 3.3 V power source voltage)
q Operating temperature range .................................... –20 to 85°C
APPLICATION
Battery-Pack, etc.
PIN CONFIGURATION (TOP VIEW)
P33/AN3
P32/AN2
P31/AN1
P30/AN0
ADVSS
ADVREF
VCC
AVCC
AVSS
ISENS0
ISENS1
DFETCNT/P45
37
38
39
40
41
42
43
44
45
46
47
48
M37517F8HP
24 P12/(LED2)
23 P13/(LED3)
22 P14/(LED4)
21 P15/(LED5)
20 P16/(LED6)
19 P17/(LED7)
18 VSS
17 XOUT
16 XIN
15 RESET
14 P20/XCOUT
13 P21/XCIN
Fig. 1 M37517F8HP pin configuration
Rev.1.01 Aug 02, 2004 page 1 of 96
Package type : 48P6Q-A
1 page  
7517 Group
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Flash Memory
The first 128 bytes and the last 2 bytes of flash memory are re-
served for device testing and the rest is user area for storing
programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
Access to this area with only 2 bytes is possible in the special
page addressing mode.
RAM
1024 bytes
000016
004016
010016
SFR area
Zero page
Flash memory
32 kbytes
044016
0FFD16
0FFF16
800016
808016
Not used
SFR area
Not used
Reserved memory area
(128 bytes)
Fig. 4 Memory map diagram
FF0016
FFD416
FFDC16
FFFE16
FFFF16
Flash memory ID code
Interrupt vector area
Reserved memory area
Special page
Rev.1.01 Aug 02, 2004 page 5 of 96
5 Page 
7517 Group
INTERRUPTS
Interrupts occur by 16 sources among 19 sources: seven external,
eleven internal, and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in-
struction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
sNotes
When the active edge of an external interrupt (INT0–INT3, SCL/
SDA, CNTR0, CNTR1) is set, the corresponding interrupt request
bit may also be set. Therefore, take the following sequence:
1. Disable the interrupt.
2. Set the interrupt edge selection register
(SCL/SDA interrupt pin polarity selection bit for SCL/SDA; the
timer XY mode register for CNTR0 and CNTR1).
3. Set the interrupt request bit to “0”.
4. Accept the interrupt.
Rev.1.01 Aug 02, 2004 page 11 of 96
11 Page | ||
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