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PDF C8051F330D Data sheet ( Hoja de datos )

Número de pieza C8051F330D
Descripción 8 kB ISP Flash MCU
Fabricantes Silicon Laboratories 
Logotipo Silicon Laboratories Logotipo



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C8051F330/1, C8051F330D
8 kB ISP Flash MCU Family
Analog Peripherals
- 10-Bit ADC (‘F330 and ‘F330D only)
Up to 200 ksps
Up to 16 external single-ended or differential inputs
VREF from internal VREF, external pin or VDD
Internal or external start of conversion source
Built-in temperature sensor
- 10-Bit Current Output DAC
(‘F330 and ‘F330D only)
- Comparator
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (0.4 µA)
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Low cost, complete development kit
Supply Voltage 2.7 to 3.6 V
- Typical operating current: 6.4 mA at 25 MHz;
9 µA at 32 kHz
- Typical stop mode current: 0.1 µA
Temperature Range: -40 to +85 °C
High Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 768 bytes internal data RAM (256 + 512)
- 8 kB Flash; In-system programmable in 512-byte
Sectors—512 bytes are reserved
Digital Peripherals
- 17 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
- Four general purpose 16-bit counter/timers
- 16-Bit programmable counter array (PCA) with three
capture/compare modules
- Real time clock mode using PCA or timer and exter-
nal clock source
Clock Sources
- Two internal oscillators:
24.5 MHz with ±2% accuracy supports crystal-less
UART operation
80/40/20/10 kHz low frequency, low power
- External oscillator: Crystal, RC, C, or clock (1 or 2
pin modes)
- Can switch between clock sources on-the-fly; useful
in power saving modes
20-Pin MLP or 20-pin DIP
ANALOG
PERIPHERALS
A 10-bit
M
U
X
200ksps
ADC
10-bit
Current
DAC
+
TEMP
SENSOR
-
VOLTAGE
COMPARATOR
DIGITAL I/O
UART
SMBus
Port 0
SPI
PCA
Port 1
Timer 0
Timer 1
P2.0
Timer 2
Timer 3
24.5 MHz PRECISION
INTERNAL OSCILLATOR
LOW FREQUENCY INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
8KB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
768 B SRAM
POR WDT
Preliminary Rev. 1.2 8/04
Copyright © 2004 by Silicon Laboratories
C8051F330/1, C8051F330D
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

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C8051F330D pdf
C8051F330/1, C8051F330D
15.3.SMBus Operation ........................................................................................... 127
15.3.1.Arbitration............................................................................................... 127
15.3.2.Clock Low Extension.............................................................................. 128
15.3.3.SCL Low Timeout................................................................................... 128
15.3.4.SCL High (SMBus Free) Timeout .......................................................... 128
15.4.Using the SMBus............................................................................................ 129
15.4.1.SMBus Configuration Register............................................................... 130
15.4.2.SMB0CN Control Register ..................................................................... 133
15.4.3.Data Register ......................................................................................... 136
15.5.SMBus Transfer Modes.................................................................................. 137
15.5.1.Master Transmitter Mode ....................................................................... 137
15.5.2.Master Receiver Mode ........................................................................... 138
15.5.3.Slave Receiver Mode ............................................................................. 139
15.5.4.Slave Transmitter Mode ......................................................................... 140
15.6.SMBus Status Decoding................................................................................. 141
16. UART0.................................................................................................................... 145
16.1.Enhanced Baud Rate Generation................................................................... 146
16.2.Operational Modes ......................................................................................... 147
16.2.1.8-Bit UART ............................................................................................. 147
16.2.2.9-Bit UART ............................................................................................. 148
16.3.Multiprocessor Communications .................................................................... 149
17. Enhanced Serial Peripheral Interface (SPI0)...................................................... 157
17.1.Signal Descriptions......................................................................................... 158
17.1.1.Master Out, Slave In (MOSI).................................................................. 158
17.1.2.Master In, Slave Out (MISO).................................................................. 158
17.1.3.Serial Clock (SCK) ................................................................................. 158
17.1.4.Slave Select (NSS) ................................................................................ 158
17.2.SPI0 Master Mode Operation ......................................................................... 159
17.3.SPI0 Slave Mode Operation ........................................................................... 161
17.4.SPI0 Interrupt Sources ................................................................................... 161
17.5.Serial Clock Timing......................................................................................... 162
17.6.SPI Special Function Registers ...................................................................... 164
18. Timers ................................................................................................................... 171
18.1.Timer 0 and Timer 1 ....................................................................................... 171
18.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 171
18.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 172
18.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 173
18.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................. 174
18.2.Timer 2 .......................................................................................................... 179
18.2.1.16-bit Timer with Auto-Reload................................................................ 179
18.2.2.8-bit Timers with Auto-Reload................................................................ 180
18.3.Timer 3 .......................................................................................................... 183
18.3.1.16-bit Timer with Auto-Reload................................................................ 183
18.3.2.8-bit Timers with Auto-Reload................................................................ 184
19. Programmable Counter Array ............................................................................. 187
Rev. 1.2
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C8051F330D arduino
C8051F330/1, C8051F330D
18. Timers
Figure 18.1. T0 Mode 0 Block Diagram.................................................................. 172
Figure 18.2. T0 Mode 2 Block Diagram.................................................................. 173
Figure 18.3. T0 Mode 3 Block Diagram.................................................................. 174
Figure 18.4. TCON: Timer Control Register ........................................................... 175
Figure 18.5. TMOD: Timer Mode Register ............................................................. 176
Figure 18.6. CKCON: Clock Control Register ........................................................ 177
Figure 18.7. TL0: Timer 0 Low Byte ....................................................................... 178
Figure 18.8. TL1: Timer 1 Low Byte ....................................................................... 178
Figure 18.9. TH0: Timer 0 High Byte...................................................................... 178
Figure 18.10. TH1: Timer 1 High Byte.................................................................... 178
Figure 18.11. Timer 2 16-Bit Mode Block Diagram ................................................ 179
Figure 18.12. Timer 2 8-Bit Mode Block Diagram .................................................. 180
Figure 18.13. TMR2CN: Timer 2 Control Register ................................................. 181
Figure 18.14. TMR2RLL: Timer 2 Reload Register Low Byte ................................ 182
Figure 18.15. TMR2RLH: Timer 2 Reload Register High Byte............................... 182
Figure 18.16. TMR2L: Timer 2 Low Byte................................................................ 182
Figure 18.17. TMR2H Timer 2 High Byte ............................................................... 182
Figure 18.18. Timer 3 16-Bit Mode Block Diagram ................................................ 183
Figure 18.19. Timer 3 8-Bit Mode Block Diagram .................................................. 184
Figure 18.20. TMR3CN: Timer 3 Control Register ................................................. 185
Figure 18.21. TMR3RLL: Timer 3 Reload Register Low Byte ................................ 186
Figure 18.22. TMR3RLH: Timer 3 Reload Register High Byte............................... 186
Figure 18.23. TMR3L: Timer 3 Low Byte................................................................ 186
Figure 18.24. TMR3H Timer 3 High Byte ............................................................... 186
19. Programmable Counter Array
Figure 19.1. PCA Block Diagram............................................................................ 187
Table 19.1. PCA Timebase Input Options .............................................................. 188
Figure 19.2. PCA Counter/Timer Block Diagram.................................................... 188
Table 19.2. PCA0CPM Register Settings for PCA Capture/Compare Modules ..... 190
Figure 19.3. PCA Interrupt Block Diagram ............................................................. 190
Figure 19.4. PCA Capture Mode Diagram.............................................................. 191
Figure 19.5. PCA Software Timer Mode Diagram .................................................. 192
Figure 19.6. PCA High-Speed Output Mode Diagram............................................ 193
Figure 19.7. PCA Frequency Output Mode ............................................................ 194
Figure 19.8. PCA 8-Bit PWM Mode Diagram ......................................................... 195
Figure 19.9. PCA 16-Bit PWM Mode...................................................................... 196
Figure 19.10. PCA Module 2 with Watchdog Timer Enabled ................................. 197
Table 19.3. Watchdog Timer Timeout Intervals1.................................................... 199
Figure 19.11. PCA0CN: PCA Control Register ...................................................... 200
Figure 19.12. PCA0MD: PCA Mode Register......................................................... 201
Figure 19.13. PCA0CPMn: PCA Capture/Compare Mode Registers..................... 202
Figure 19.14. PCA0L: PCA Counter/Timer Low Byte............................................. 203
Figure 19.15. PCA0H: PCA Counter/Timer High Byte ........................................... 203
Figure 19.16. PCA0CPLn: PCA Capture Module Low Byte ................................... 203
Rev. 1.2
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