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PDF XC2S200E Data sheet ( Hoja de datos )

Número de pieza XC2S200E
Descripción (XC2SxxxE) Spartan IIE 1.8V FPGA Family
Fabricantes Xilinx 
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0
R Spartan-IIE 1.8V FPGA Family:
Complete Data Sheet
DS077 July 28, 2004
0 0 Product Specification
This document includes all four modules of the Spartan™-IIE FPGA data sheet.
Module 1:
Module 3:
Introduction and Ordering Information DC and Switching Characteristics
DS077-1 (v2.2) July 28, 2004
6 pages
DS077-3 (v2.1) July 9, 2003
22 pages
• Introduction
• DC Specifications
• Features
• General Overview
m• Product Availability
o• User I/O Chart
Ordering Information
.cModule 2:
UFunctional Description
DS077-2 (v2.1) July 9, 2003
t420 pages
• Architectural Description
e- Spartan-IIE Array
e- Input/Output Block
- Configurable Logic Block
h- Block RAM
- Clock Distribution: Delay-Locked Loop
S- Boundary Scan
ta• Development System
aConfiguration
- Absolute Maximum Ratings
- Recommended Operating Conditions
- DC Characteristics
- Power-On Requirements
- DC Input and Output Levels
• Switching Characteristics
- Pin-to-Pin Parameters
- IOB Switching Characteristics
- Clock Distribution Characteristics
- DLL Timing Parameters
- CLB Switching Characteristics
- Block RAM Switching Characteristics
- TBUF Switching Characteristics
- JTAG Switching Characteristics
- Configuration Switching Characteristics
Module 4:
Pinout Tables
DS077-4 (2.1) February 14, 2003
54 pages
• Pin Definitions
• Pinout Tables
w.DIMPORTANT NOTE: The Spartan-IIE 1.8V FPGA data sheet is created and published in separate modules. This complete
version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin
wat 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy
wnavigation in this volume.
heet4U.com© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
taSAll other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
.DaDS077 July 28, 2004
wwwProduct Specification
www.xilinx.com
1-800-255-7778

1 page




XC2S200E pdf
Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information
R
Ordering Information
Spartan-IIE devices are available in both standard and Pb-free packaging options for all device/package combinations. The
Pb-free packages include a special "G" character in the ordering code.
Standard Packaging
Pb-Free Packaging
Example: XC2S50E -6 PQ 208 C
Device Type
Speed Grade
Package Type
Temperature Range
Number of Pins
DS077-1_03a_072004
Example: XC2S50E -6 PQ G 208 C
Device Type
Speed Grade
Package Type
Temperature Range
Number of Pins
Pb-free
DS077-1_03b_072004
Device Ordering Options
Device
Speed Grade
Package Type / Number of Pins
XC2S50E
XC2S100E
-6 Standard Performance
-7 Higher Performance(1)
TQ(G)144 144-pin Plastic Thin QFP
PQ(G)208 208-pin Plastic QFP
XC2S150E
FT(G)256 256-ball Fine Pitch BGA
XC2S200E
FG(G)456 456-ball Fine Pitch BGA
XC2S300E
FG(G)676 676-ball Fine Pitch BGA
XC2S400E
XC2S600E
Notes:
1. The -7 speed grade is exclusively available in the Commercial temperature range.
2. See www.xilinx.com for information on automotive temperature range devices.
Device Part Marking
Temperature Range (TJ)(2)
C = Commercial
0°C to +85°C
I = Industrial
–40°C to +100°C
Device Type
Package
Speed
Operating Range
R
SPARTAN R
XC2S50E
PQ208xxx0425
xxxxxxxxx
6C
Date Code
Lot Code (numeric)
Sample package with part marking
for XC2S50E-6PQ208C.
ds077-1_02_072804
4
www.xilinx.com
DS077-1 (v2.2) July 28, 2004
1-800-255-7778
Product Specification

5 Page





XC2S200E arduino
Spartan-IIE 1.8V FPGA Family: Functional Description
R
VREF pins within a bank are interconnected internally and
consequently only one VREF voltage can be used within
each bank. All VREF pins in the bank, however, must be con-
nected to the external voltage source for correct operation.
In a bank, inputs requiring VREF can be mixed with those
that do not but only one VREF voltage may be used within a
bank. The VCCO and VREF pins for each bank appear in the
device pinout tables.
Within a given package, the number of VREF and VCCO pins
can vary depending on the size of device. In larger devices,
more I/O pins convert to VREF pins. Since these are always
a superset of the VREF pins used for smaller devices, it is
possible to design a PCB that permits migration to a larger
device. All VREF pins for the largest device anticipated must
be connected to the VREF voltage, and not used for I/O.
Table 3: I/O Banking
Package
TQ144, PQ208
FT256, FG456,
FG676
VCCO Banks
VREF Banks
Interconnected as 1
8 independent
8 independent
8 independent
See Xilinx Application Note XAPP179 for more information
on I/O resources.
Hot Swap, Hot Insertion, Hot Socketing Support
The I/O pins support hot swap — also called hot insertion
and hot socketing — and are considered CompactPCI
Friendly according to the PCI Bus v2.2 Specification. Con-
sequently, an unpowered Spartan-IIE FPGA can be
plugged directly into a powered system or backplane with-
out affecting or damaging the system or the FPGA. The hot
swap functionality is built into every XC2S150E,
XC2S400E, and XC2S600E device. All other Spartan-IIE
devices built after Product Change Notice PCN2002-05 also
include hot swap functionality.
To support hot swap, Spartan-IIE devices include the follow-
ing I/O features.
• Signals can be applied to Spartan-IIE I/O pins before
powering the FPGA’s VCCINT or VCCO supply inputs.
• Spartan-IIE I/O pins are high-impedance (i.e.,
three-stated) before and throughout the power-up and
configuration processes when employing a
configuration mode that does not enable the
preconfiguration weak pull-up resistors (see Table 9,
page 13).
• There is no current path from the I/O pin back to the
VCCINT or VCCO voltage supplies.
• Spartan-IIE FPGAs are immune to latch-up during hot
swap.
Once connected to the system, each pin adds a small
amount of capacitance (CIN). Likewise, each I/O consumes
a small amount of DC current, equivalent to the input leak-
age specification (IL). There also may be a small amount of
temporary AC current (IHSPO) when the pin input voltage
exceeds VCCO plus 0.4V, which lasts less than 10 ns.
A weak-keeper circuit within each user-I/O pin is enabled
during the last frame of configuration data and has no
noticeable effect on robust system signals driven by an
active driver or a strong pull-up or pull-down resistor.
Undriven or floating system signals may be affected. The
specific effect depends on how the I/O pin is configured.
User-I/O pins configured as outputs or enabled outputs
have a weak pull-up resistor to VCCO during the last config-
uration frame. User-I/O pins configured as inputs or bidirec-
tional I/Os have weak pull-down resistors. The weak-keeper
circuit turns off when the DONE pin goes High, provided
that it is not used in the configured application.
Configurable Logic Block
The basic building block of the Spartan-IIE CLB is the logic
cell (LC). An LC includes a 4-input function generator, carry
logic, and storage element. The output from the function
generator in each LC drives the CLB output or the D input of
the flip-flop. Each Spartan-IIE CLB contains four LCs, orga-
nized in two similar slices; a single slice is shown in
Figure 4.
In addition to the four basic LCs, the Spartan-IIE CLB con-
tains logic that combines function generators to provide
functions of five or six inputs.
Look-Up Tables
Spartan-IIE function generators are implemented as 4-input
look-up tables (LUTs). In addition to operating as a function
generator, each LUT can provide a 16 x 1-bit synchronous
RAM. Furthermore, the two LUTs within a slice can be com-
bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,
or a 16 x 1-bit dual-port synchronous RAM.
The Spartan-IIE LUT can also provide a 16-bit shift register
that is ideal for capturing high-speed or burst-mode data.
This mode can also be used to store data in applications
such as Digital Signal Processing.
Storage Elements
Storage elements in the Spartan-IIE slice can be configured
either as edge-triggered D-type flip-flops or as level-sensi-
tive latches. The D inputs can be driven either by function
generators within the slice or directly from slice inputs,
bypassing the function generators.
In addition to Clock and Clock Enable signals, each slice
has synchronous set and reset signals (SR and BY). SR
forces a storage element into the initialization state speci-
fied for it in the configuration. BY forces it into the opposite
state. Alternatively, these signals may be configured to
operate asynchronously.
All control signals are independently invertible, and are
shared by the two flip-flops within the slice.
4
www.xilinx.com
DS077-2 (v2.1) July 9, 2003
1-800-255-7778
Product Specification

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