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Número de pieza ICS343
Descripción Field Programmable Triple Output SS VersaClock Synthesizer
Fabricantes Integrated Circuit Solution 
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ICS343
Field Programmable Triple Output SS VersaClock Synthesizer
Description
The ICS343 is a low cost, triple-output, field program-
mable clock synthesizer. The ICS343 can generate
three output frequencies from 250 kHz to 200 MHz,
using up to three independently configurable PLLs.
The outputs may employ Spread Spectrum techniques
to reduce system electro-magnetic interference (EMI).
Using ICS’ VersaClock™ software to configure the PLL
and output, the ICS343 contains a One-Time Program-
mable (OTP) ROM to allow field programmability. Using
Phase-Locked Loop (PLL) techniques, the device runs
from a standard fundamental mode, inexpensive crys-
tal, or clock. It can replace multiple crystals and oscilla-
tors, saving board space and cost.
The device also has a power down feature that
tri-states the clock outputs and turns off the PLLs when
the PDTS pin is taken low.
The ICS343 is also available in factory-programmed
custom versions for high-volume applications.
Features
8-pin SOIC package
Highly accurate frequency generation
M/N Multiplier PLL: M = 1...2048, N = 1...1024
Output clock frequencies up to 200 MHz
Spread spectrum capability for lower system EMI
Center or Down Spread up to 4% total
Selectable 32 kHz or 120 kHz modulation
Input crystal frequency from 5 to 27 MHz
Input clock frequency from 2 to 50 MHz
Operating voltage of 3.3 V, using advanced, low
power CMOS process
For one output clock, use the ICS341. For two output
clocks, see the ICS342. For more than three outputs,
see the ICS345 or ICS348.
Available in Pb (lead) free packaging
Block Diagram
VDD
Crystal or
clock input
X1/ICLK
X2
OTP ROM
with PLL
Divider
Values
Crystal
Oscillator
External capacitors are
required with a crystal input.
PLL Clock Synthesis,
Spred Spectrum and
Control Circuitry
CLK1
CLK2
CLK3
GND
PDTS (both outputs and PLL)
MDS 343 F
1
Revision 090704
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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ICS343 pdf
ICS343
Field Programmable Triple Output SS VersaClock
Parameter
Symbol
Conditions
Output High Voltage
(CMOS High)
VOH IOH = -4 mA
Output High Voltage
Output Low Voltage
Short Circuit Current
Nominal Output
Impedance
VOH
VOL
IOS
ZO
IOH = -12 mA
IOL = 12 mA
Internal Pull-up Resistor
Internal Pull-down Resistor
Input Capacitance
RPUP
RPD
CIN
PDTS pin
CLK output
Inputs
Min. Typ.
VDD-0.4
Max. Units
V
2.4 V
0.4 V
±70 mA
20
250 k
525 k
4 pF
Note 1: Example with 25 MHz crystal input with three outputs of 33.3 MHz, no load, and VDD = 3.3 V.
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Frequency
FIN Fundamental Crystal
Input Clock
5
2
27 MHz
50 MHz
Output Frequency
0.25 200 MHz
Output Rise Time
Output Fall Time
Duty Cycle
tOR 20% to 80%, Note 1
tOF 80% to 20%, Note 1
Note 2
1
1
40 49-51 60
ns
ns
%
Power-up time
PLL lock time from
power-up, Note 3
4 10 ms
PDTS goes high until
stable CLK output, Spread
Spectrum Off, Note 3
0.2 2 ms
PDTS goes high until
stable CLK output, Spread
Spectrum On, Note 3
4 7 ms
One Sigma Clock Period Jitter
Configuration Dependent
50 ps
Maximum Absolute Jitter
tja Deviation from Mean.
Configuration Dependent
+200
ps
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%.
Note 3: ICS test mode output occurs for first 170 clock cycles on CLK3 for each PLL powered up.
MDS 343 F
5
Revision 090704
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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