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PDF ICS345 Data sheet ( Hoja de datos )
| Número de pieza | ICS345 | |
| Descripción | Triple PLL Field Programmable SS VersaClock Synthesizer | |
| Fabricantes | Integrated Circuit Systems | |
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ICS345
Triple PLL Field Programmable SS VersaClock Synthesizer
Description
The ICS345 field programmable clock synthesizer
generates up to nine high-quality, high-frequency clock
outputs including multiple reference clocks from a
low-frequency crystal or clock input. It is designed to
replace crystals and crystal oscillators in most
electronic systems.
Using ICS’ VersaClockTM software to configure PLLs
and outputs, the ICS345 contains a One-Time
Programmable (OTP) ROM to allow field
programmability. Programming features include eight
selectable configuration registers, up to two sets of four
low-skew outputs, and optional Spread Spectrum
outputs.
Using Phase-Locked Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal, or clock. It can replace multiple
crystals and oscillators, saving board space and cost.
The ICS345 is also available in factory programmed
custom versions for high-volume applications.
Features
• Packaged as 20-pin SSOP (QSOP)
• Spread spectrum capability
• Eight addressable registers
• Replaces multiple crystals and oscillators
• Output frequencies up to 200 MHz at 3.3 V
• Input crystal frequency of 5 to 27 MHz
• Input clock frequency of 2 to 50 MHz
• Up to nine reference outputs
• Up to two sets of four low-skew outputs
• Operating voltages of 3.3 V
• Advanced, low-power CMOS process
• For one output clock, use the ICS341. For two output
clocks, see the ICS342. For three output clocks, see
the ICS343. For more than three outputs, see the
ICS345 or ICS348.
• Available in Pb (lead) free packaging
Block Diagram
S2:S0
3
OTP
ROM
w ith
PLL
V a lu e s
Crystal or
clock input
X1/ICLK
X2
Crystal
O s c illa to r
External capacitors are
required with a crystal input.
VDD 3
PLL1 with
Spread
S p e c tru m
PLL2
PLL3
Divide
Logic
and
O u tp u t
E n ab le
Control
GND 2
PDTS
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
MDS 345 D
1
Revision 090704
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
1 page  
ICS345
Triple PLL Field Programmable SS VersaClock Synthesizer
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (ICS345RP)
Ambient Operating Temperature (ICS345RIP)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
Min.
0
-40
+3.15
Typ.
+3.3
Max.
+70
+85
+3.45
4
Units
°C
°C
V
ms
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85°C
Parameter
Symbol
Conditions
Min.
Operating Voltage
VDD
3.15
Configuration Dependent -
See VersaClockTM
Estimates
Operating Supply Current IDD Nine 33.3333 MHz outs,
Input High Voltage
PDTS = 1, no load, Note 1
PDTS = 0, no load, Note 1
Input High Voltage
VIH S2:S0
2
Input Low Voltage
VIL S2:S0
Input High Voltage, PDTS VIH
VDD-0.5
Input Low Voltage, PDTS VIL
Input High Voltage
VIH ICLK
VDD/2+1
Input Low Voltage
VIL ICLK
Output High Voltage
(CMOS High)
VOH IOH = -4 mA
VDD-0.4
Output High Voltage
Output Low Voltage
Short Circuit Current
Nominal Output
Impedance
VOH
VOL
IOS
ZO
IOH = -12 mA
IOL = 12 mA
2.4
Internal pull-up resistor
Internal pull-down
resistor
RPUS
RPD
S2:S0, PDTS
CLK outputs
Input Capacitance
CIN Inputs
Typ.
23
20
±70
20
250
525
4
Max.
3.45
Units
V
mA
mA
0.4
0.4
VDD/2-1
µA
V
V
V
V
V
V
V
V
0.4 V
mA
Ω
kΩ
kΩ
pF
Note 1: Example with 25 MHz crystal input with nine outputs of 33.3 MHz, no load, and VDD = 3.3 V.
MDS 345 D
5
Revision 090704
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet ICS345.PDF ] | |
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