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PDF 89C51RD2 Data sheet ( Hoja de datos )
| Número de pieza | 89C51RD2 | |
| Descripción | T89C51RD2 | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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T89C51RD2
0 to 40MHz Flash Programmable 8-bit Microcontroller
1. Description
ATMEL Wireless and Microcontrollers T89C51RD2 is
high performance CMOS Flash version of the 80C51
CMOS single chip 8-bit microcontroller. It contains a
64 Kbytes Flash memory block for program and for data.
The 64 Kbytes Flash memory can be programmed either
in parallel mode or in serial mode with the ISP capability
or with software. The programming voltage is internally
generated from the standard VCC pin.
The T89C51RD2 retains all features of the ATMEL
Wireless and Microcontrollers 80C52 with 256 bytes of
www.DataShineteetr4nUa.lcoRmAM, a 7-source 4-level interrupt controller and
three timer/counters.
In addition, the T89C51RD2 has a Programmable
Counter Array, an XRAM of 1024 bytes, an EEPROM
of 2048 bytes, a Hardware Watchdog Timer, a more
versatile serial channel that facilitates multiprocessor
communication (EUART) and a speed improvement
mechanism (X2 mode). Pinout is either the standard 40/
44 pins of the C52 or an extended version with 6 ports
in a 64/68 pins package.
The fully static design of the T89C51RD2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The T89C51RD2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the peripherals and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
The added features of the T89C51RD2 makes it more
powerful for applications that need pulse width
modulation, high speed I/O and counting capabilities
such as alarms, motor control, corded phones, smart card
readers.
2. Features
• 80C52 Compatible
• 8051 pin and instruction compatible
• Four 8-bit I/O ports (or 6 in 64/68 pins packages)
• Three 16-bit timer/counters
• 256 bytes scratch pad RAM
• 7 Interrupt sources with 4 priority levels
• ISP (In System Programming) using standard VCC
power supply.
• Boot FLASH contains low level FLASH
programming routines and a default serial loader
• High-Speed Architecture
• 40 MHz in standard mode
• 20 MHz in X2 mode (6 clocks/machine cycle)
• 64K bytes on-chip Flash program / data Memory
• Byte and page (128 bytes) erase and write
• 10k write cycles
• On-chip 1024 bytes expanded RAM (XRAM)
• Software selectable size (0, 256, 512, 768, 1024
bytes)
• 768 bytes selected at reset for T87C51RD2
compatibility
• Dual Data Pointer
• Variable length MOVX for slow RAM/peripherals
• Improved X2 mode with independant selection for
CPU and each peripheral
• 2 k bytes EEPROM block for data storage
• 100K Write cycle
• Programmable Counter Array with:
• High Speed Output,
• Compare / Capture,
• Pulse Width Modulator,
• Watchdog Timer Capabilities
• Asynchronous port reset
• Full duplex Enhanced UART
• Low EMI (inhibit ALE)
• Hardware Watchdog Timer (One-time enabled with
Reset-Out)
• Power control modes:
• Idle Mode.
• Power-down mode.
Rev. F - 15 February, 2001
1
1 page  
5. Pin Configuration
P1.0/T2 1
P1.1/T2EX 2
P1.2/ECI
P1.3CEX0
P1.4/CEX1
P1.5/CEX2
3
4
5
6
P1.6/CEX3 7
P1.7CEX4 8
RST 9
P3.0/RxD 10
P3.1/TxD
P3.2/INT0
P3.3/INT1
11
12
13
P3.4/T0 14
P3.5/T1 15
P3.6/WR 16
P3.7/RD
www.DataSheet4XUT.AcLo2m
XTAL1
VSS
17
18
19
20
PDIL
40 VCC
39 P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
36 P0.3/AD3
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
31 EA
30 ALE/PROG
29 PSEN
28 P2.7/AD15
27 P2.6/AD14
26 P2.5/AD13
25 P2.4/AD12
24 P2.3/AD11
23 P2.2/AD10
22 P2.1/AD9
21 P2.0/AD8
T89C51RD2
P1.5/CEX2
P1.6/CEX3
P1.7/CEx4
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 PLCC 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P1.5/CEX2
P1.6/CEX3
P1.7/CEX4
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6
VQFP44 1.4
28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
*NIC: No Internal Connection
Rev. F - 15 February, 2001
5
5 Page 
T89C51RD2
XTAL1
XTAL1:2
X2 bit
CPU clock
STD Mode
X2 Mode
STD Mode
Figure 2. Mode Switching Waveforms
The X2 bit in the CKCON register (See Table 2.) allows to switch from 12 clock periods per instruction to 6
www.DcaltaoSckhepete4rUio.cdosmand vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the
X2 feature (X2 mode).
The T0X2, T1X2, T2X2, SiX2, PcaX2 and WdX2 bits in the CKCON register (See Table 2.) allow to switch from
standard peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods
per peripheral clock cycle). These bits are active only in X2 mode.
More information about the X2 mode can be found in the application note ANM072 "How to take advantage of
the X2 features in TS80C51 microcontroller?"
CKCON - Clock Control Register (8Fh)
765
-
WdX2
PcaX2
Table 2. CKCON Register
4
SiX2
3
T2X2
2
T1X2
1
T0X2
0
X2
Bit
Number
7
6
5
4
3
2
Bit
Mnemonic
Description
- Reserved
WdX2
Watchdog clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
PcaX2
Programmable Counter Array clock (This control bit is validated when the CPU clock X2 is set; when X2 is
low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
SiX2
Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the CPU clock X2 is set; when X2
is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
T2X2
Timer2 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
T1X2
Timer1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
11 Rev. F - 15 February, 2001
11 Page | ||
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