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PDF M12L64164A Data sheet ( Hoja de datos )
| Número de pieza | M12L64164A | |
| Descripción | 1M x 16-Bit x 4-Bank SDRAM | |
| Fabricantes | Elite Semiconductor | |
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ESMT
SDRAM
M12L64164A
1M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
ORDERING INFORMATION
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
54 Pin TSOP (Type II)
(400mil x 875mil )
PRODUCT NO. MAX FREQ. PACKAGE Comments
MRS cycle with address key programs
- CAS Latency (2 & 3)
M12L64164A-6T
166MHz TSOP II Non-Pb-free
- Burst Length (1, 2, 4, 8 & full page)
M12L64164A-7T
143MHz TSOP II Non-Pb-free
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
mDQM for masking
Auto & self refresh
o15.6 µ s refresh interval
M12L64164A-6TG
M12L64164A-7TG
166MHz
143MHz
TSOP II
TSOP II
Pb-free
Pb-free
.cGENERAL DESCRIPTION
UThe M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by
t416 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
eePIN ASSIGNMENT
hTop View
SVDD
taDQ0
VDDQ
DQ1
aDQ2
VSSQ
.D DQ3
DQ4
VDDQ
DQ5
w DQ6
VSSQ
w DQ7
VDD
w LDQM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
54 VSS
53 DQ15
52 VS SQ
51 DQ14
50 DQ13
49 VDDQ
48 DQ12
47 DQ11
46 VS SQ
45 DQ10
44 DQ9
43 VDDQ
42 DQ8
41 VSS
40 N C
W E 16
39 U D Q M
C AS 17
38 CLK
R AS 18
37 CKE
CS 19
36 N C
A13 20
35 A11
A12 21
34 A9
A10/AP 22
33 A8
A0 23
32 A7
A1 24
31 A6
A2 25
30 A5
A3 26
29 A4
VDD 27
28 VSS
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2005
Revision: 2.4
1/44
1 page  
ESMT
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V ，TA = 0 to 70 °C )
PARAMETER
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall-time
Output timing measurement reference level
Output load condition
VALUE
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Output
870Ω
3.3V
1200Ω
VOH (DC) =2.4V , IOH = -2 mA
50pF
VOL (DC) =0.4V , IOL = 2 mA
Output
Z0 =50Ω
M12L64164A
UNIT
V
V
ns
V
Vtt = 1.4V
50Ω
50pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
PARAMETER
SYMBOL
Row active to row active delay
tRRD(min)
RAS to CAS delay
tRCD(min)
Row precharge time
tRP(min)
Row active time
tRAS(min)
tRAS(max)
Row cycle time
@ Operating
@ Auto refresh
tRC(min)
tRFC(min)
Last data in to col. address delay
tCDL(min)
Last data in to row precharge
tRDL(min)
Last data in to burst stop
tBDL(min)
Col. address to col. address delay
tCCD(min)
Number of valid
Output data
CAS latency = 3
CAS latency = 2
VERSION
-6 -7
12 14
18 20
18 20
40 42
100
58 63
60 70
1
2
1
1
2
1
UNIT
ns
ns
ns
ns
us
ns
ns
CLK
CLK
CLK
CLK
ea
NOTE
1
1
1
1
1
1,5
2
2
2
3
4
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete with.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given tRFC after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2005
Revision: 2.4
5/44
5 Page 
ESMT
DEVICE OPERATIONS
CLOCK (CLK)
The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with CKE
high all inputs are assumed to be in valid state (low or high)
for the duration of setup and hold time around positive edge
of the clock for proper functionality and Icc specifications.
CLOCK ENABLE(CKE)
The clock enable (CKE) gates the clock onto SDRAM. If
CKE goes low synchronously with clock (set-up and hold
time same as other inputs), the internal clock suspended
from the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes
low. When all banks are in the idle state and CKE goes low
synchronously with clock, the SDRAM enters the power
down mode from the next clock cycle. The SDRAM remains
in the power down mode ignoring the other inputs as long as
CKE remains low. The power down exit is synchronous as
the internal clock is suspended. When CKE goes high at
least “1CLK + tSS” before the high going edge of the clock,
then the SDRAM becomes active from the same clock edge
accepting all the input commands.
BANK ADDRESSES (A13~A12)
This SDRAM is organized as four independent banks of
1,048,576 words x 16 bits memory arrays. The A13~A12
inputs are latched at the time of assertion of RAS and
CAS to select the bank to be used for the operation. The
banks addressed A13~A12 are latched at bank active, read,
write, mode register set and precharge operations.
ADDRESS INPUTS (A0~A11)
The 20 address bits are required to decode the 1,048,576
word locations are multiplexed into 12 address input pins
(A0~A11). The 12 row addresses are latched along with
RAS and A13~A12 during bank active command. The 8 bit
column addresses are latched along with CAS , WE and
A13~A12 during read or with command.
NOP and DEVICE DESELECT
When RAS , CAS and WE are high, The SDRAM
performs no operation (NOP). NOP does not initiate any new
operation, but is needed to complete operations which
require more than single clock cycle like bank activate, burst
read, auto refresh, etc. The device deselect is also a NOP
and is entered by asserting CS high. CS high disables
the command decoder so that RAS , CAS , WE and all
the address inputs are ignored.
Elite Semiconductor Memory Technology Inc.
M12L64164A
POWER-UP
1.Apply power and start clock, Attempt to maintain CKE
= “H”, DQM = “H” and the other pins are NOP
condition at the inputs.
2.Maintain stable power, stable clock and NOP input
condition for minimum of 200us.
3.Issue precharge commands for both banks of the
devices.
4.Issue 2 or more auto-refresh commands.
5.Issue a mode register set command to initialize the
mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the
various operating modes of SDRAM. It programs the
CAS latency, burst type, burst length, test mode and
various vendor specific options to make SDRAM useful
for variety of different applications. The default value of
the mode register is not defined, therefore the mode
register must be written after power up to operate the
SDRAM. The mode register is written by asserting low
on CS , RAS , CAS and WE (The SDRAM should
be in active mode with CKE already high prior to writing
the mode register). The state of address pins A0~A11
and A13~A12 in the same cycle as CS , RAS , CAS
and WE going low is the data written in the mode
register. Two clock cycles is required to complete the
write in the mode register. The mode register contents
can be changed using the same command and clock
cycle requirements during operation as long as all banks
are in the idle state. The mode register is divided into
various fields into depending on functionality. The burst
length field uses A0~A2, burst type uses A3, CAS
latency (read latency from column address) use A4~A6,
test mode use A7~A8, vendor specific options use A9,
A10~A11 and A12~A13. A7~A8, A10/AP~A11 and
A13~A12 must be set to low for normal SDRAM
operation. Refer to the table for specific codes for
various burst length, burst type and CAS latencies.
Publication Date: Jul. 2005
Revision: 2.4
11/44
11 Page | ||
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| PDF Descargar | [ Datasheet M12L64164A.PDF ] | |
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