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PDF M12L128324A Data sheet ( Hoja de datos )
| Número de pieza | M12L128324A | |
| Descripción | Dynamic RAM | |
| Fabricantes | Elite Semiconductor | |
| Logotipo |  |
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ESMT
Revision History
Revision 0.1(May. 13 2005)
-Original
Revision 0.2 (Aug. 08 2005)
-Delete Non-Pb-free of ordering information
Preliminary M12L128324A
www.DataSheet4U.com
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2005
Revision: 0.2
1/46
1 page  
ESMT
Preliminary M12L128324A
PIN
DQM0~3
DQ0 ~ DQ31
VDD / VSS
VDDQ / VSSQ
N.C
NAME
Data Input / Output Mask
Data Input / Output
Power Supply / Ground
Data Output Power / Ground
No Connection
INPUT FUNCTION
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD 1 W
Short circuit current
IOS 50 mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 °C )
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
Symbol
VDD, VDDQ
VIH
VIL
VOH
VOL
IIL
IOL
Min
3.0
2.0
-0.3
2.4
-
-5
-5
Typ Max
3.3 3.6
3.0 VDD+0.3
0 0.8
--
- 0.4
-5
-5
Note:
1. VIH(max) = 4.6V AC for pulse width ≤ 10ns acceptable.
2. VIL(min) = -1.5V AC for pulse width ≤ 10ns acceptable.
3. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V.
4. Dout is disabled , 0V ≤ VOUT ≤ VDD.
Unit
V
V
V
V
V
μA
μA
Note
1
2
IOH = -2mA
IOL = 2mA
3
4
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2005
Revision: 0.2
5/46
5 Page 
ESMT
Preliminary M12L128324A
If both BA1 is “High” and BA0 is “Low” at read ,write , row active and precharge ,bank C is selected.
If both BA1 and BA0 are “High” at read ,write , row active and precharge ,bank D is selected
If A10/AP is “High” at row precharge , BA1 and BA0 is ignored and all banks are selected.
5.During burst read or write with auto precharge. new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
A11
RFU
BA0~BA1
RFU
A10/AP
RFU
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
W.B.L
TM
CAS Latency BT Burst Length
Test Mode
A8 A7
Type
A6
0 0 Mode Register Set 0
01
Reserved
0
10
Reserved
0
11
Reserved
0
Write Burst Length
1
A9 Length
1
0 Burst 1
1 Single Bit 1
CAS Latency
A5 A4 Latency
0 0 Reserved
01
1
10
2
11
3
0 0 Reserved
0 1 Reserved
1 0 Reserved
1 1 Reserved
Burst Type
Burst Length
A3 Type A2 A1 A0 BT = 0 BT = 1
0 Sequential 0 0 0
1
1
1 Interleave 0 0 1
2
2
010
4
4
011
8
8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved
Full Page Length : 256
POWER UP SEQUENCE
1.Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP condition at the inputs.
2. Maintain stable power , stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note :
1. RFU(Reserved for future use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “ Burst Read single Bit Write” function will be enabled.
3. The full column burst (256 bit) is available only at sequential mode of burst type.
Elite Semiconductor Memory Technology Inc.
Publication Date: Aug. 2005
Revision: 0.2
11/46
11 Page | ||
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| PDF Descargar | [ Datasheet M12L128324A.PDF ] | |
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