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PDF SCN68661 Data sheet ( Hoja de datos )

Número de pieza SCN68661
Descripción (SCN2661 / SCN68661) Enhanced programmable communications interface EPCI
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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Philips Semiconductors
Enhanced programmable communications
interface (EPCI)
Product specification
SCN2661/SCN68661
DESCRIPTION
The Philips Semiconductors SCN2661 EPCI is a universal
synchronous/asynchronous data communications controller chip
that is an enhanced version of the SCN2651. It interfaces easily to
all 8-bit and 16-bit microprocessors and may be used in a polled or
interrupt driven system environment. The SCN2661 accepts
programmed instructions from the microprocessor while supporting
many serial data communications disciplines —synchronous and
asynchronous — in the full- or half-duplex mode. Special support
for BISYNC is provided.
The EPCI serializes parallel data characters received from the
microprocessor for transmission. Simultaneously, it can receive
serial data and convert it into parallel data characters for input to the
microcomputer.
The SCN2661 contains a baud rate generator which can be
programmed to either accept an external clock or to generate
internal transmit or receive clocks. Sixteen different baud rates can
be selected under program control when operating in the internal
clock mode. Each version of the EPCI (A, B, C) has a different set
of baud rates.
FEATURES
Synchronous operation
5- to 8-bit characters plus parity
Single or double SYN operation
Internal or external character synchronization
Transparent or non-transparent mode
Transparent mode DLE stuffing (Tx) and detection (Rx)
Automatic SYN or DLE-SYN insertion SYN, DLE and DLESYN
stripping
Odd, even, or no parity
Local or remote maintenance loopback mode
Baud rate: DC to 1Mbps (1X clock)
Asynchronous operation
5- to 8-bit characters plus parity
1, 1-1/2 or 2 stop bits transmitted
Odd, even, or no parity
Parity, overrun and framing error detection
Line break detection and generation
False start bit detection
Automatic serial echo mode (echoplex)
Local or remote maintenance loopback mode
Baud rate: DC to 1Mbps
(1X clock)
DC to 62.5kbps (16X clock)
DC to 15.625kbps
(64X clock)
OTHER FEATURES
Internal or external baud rate clock
3 baud rate sets
16 internal rates for each set
Double-buffered transmitter and receiver
PIN CONFIGURATIONS
D2 1
28 D1
D3 2
27 D0
RxD 3
GND 4
26 VCC
25 RxC/BKDET
D4 5
24 DTR
D5 6
23 RTS
D6 7
22 DSR
DIP
D7 8
21 RESET
TxC/XSYNC 9
20 BRCLK
A1 10
19 TxD
CE 11
18 TxEMT/DSCHG
A0 12
17 CTS
R/W 13
16 DCD
RxRDY 14
15 TxRDY
INDEX
CORNER
4 1 26
5 25
PLCC
11 19
12 18
TOP VIEW
NOTE:
Pin Functions the same as 28-pin DIP.
Dynamic character length switching
Full- or half-duplex operation
TTL compatible inputs and outputs
RxC and TxC pins are short-circuit protected
Single +5V power supply
No system clock required
SD00077
APPLICATIONS
Intelligent terminals
Network processors
Front-end processors
Remote data concentrators
Computer-to-computer links
Serial peripherals
BISYNC adaptors
1994 Apr 27
1 853-1070 12793

1 page




SCN68661 pdf
Philips Semiconductors
Enhanced programmable communications
interface (EPCI)
Product specification
SCN2661/SCN68661
the communication technique) and outputs a composite serial
stream of data on the TxD output pin.
Modem Control
The modern control section provides interfacing for three input
signals and three output signals used for “handshaking” and status
indication between the CPU and a modem.
SYN/DLE Control
This section contains control circuitry and three 8-bit registers
storing the SYN1, SYN2, and DLE characters provided by the CPU.
These registers are used in the synchronous mode of operation to
provide the characters required for synchronization, idle fill and data
transparency.
Table 1. Baud Rate Generator Characteristics
68661A (BRCLK = 4.9152MHz)
MR23–20
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
BAUD RATE
50
75
110
134.5
150
200
300
600
1050
1200
1800
2000
2400
4800
9600
19200
ACTUAL FREQUENCY
16X CLOCK
0.8kHz
1.2
1.7598
2.152
2.4
3.2
4.8
9.6
16.8329
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2
PERCENT
ERROR
–0.01
0.196
–0.19
–0.26
DIVISOR
6144
4096
2793
2284
2048
1536
1024
512
292
256
171
154
128
64
32
16
68661B (BRCLK = 4.9152MHz)
MR23–20
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
BAUD RATE
45.5
50
75
110
134.5
150
300
600
1200
1800
2000
2400
4800
9600
19200
38400
ACTUAL FREQUENCY
16X CLOCK
0.7279kHz
0.8
1.2
1.7598
2.152
2.4
4.8
9.6
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2
614.4
PERCENT
ERROR
0.005
–0.01
–0.19
–0.26
DIVISOR
6752
6144
4096
2793
2284
2048
1024
512
256
171
154
128
64
32
16
8
1994 Apr 27
5

5 Page





SCN68661 arduino
Philips Semiconductors
Enhanced programmable communications
interface (EPCI)
Product specification
SCN2661/SCN68661
Table 8. Status Register (SR)
SR7 SR6 SR5
Data Set
Ready
0 = DSR input
is High
1 = DSR input
is Low
Data Carrier
Detect
0 = DCD input
is High
1 = DCD input
is Low
FE/SYN
Detect
Async:
0 = Normal
1 = Framing
error
Sync:
0 = Normal
1 = SYN
detected
SR4
Overrun
0 = Normal
1 = Overrun
error
SR3 SR2
PE/DLE
Detect
TxEMT
DSCHG
Async:
0 = Normal
1 = Parity error
Sync:
0 = Normal
1 = Parity error
or DLE
received
0 = Normal
1 = Change in
DSR or
DCD, or
transmit
shift
register is
empty
SR1
RxRDY
0 = Receive
holding
register
empty
1 = Receive
holding
register
has data
SR0
TxRDY
0 = Transmit
holding
register
busy
1 = Transmit
holding
register
empty
Mode Register 2 (MR2)
Table 6 illustrates mode register 2. MR23, MR22, MR21 and MR20
control the frequency of the internal baud rate generator (BRG).
Sixteen rates are selectable for each EPCI version (–1,–2,–3).
Versions 1 and 2 specify a 4.9152MHz TTL input at BRCLK (pin 20);
version 3 specifies a 5.0688MHz input which is identical to the
Philips Semiconductors 2651. MR23 – 20 are don’t cares if external
clocks are selected (MR25 – MR24 = 0). The individual rates are
given in Table 1.
MR24 – MR27 select the receive and transmit clock source (either
the BRG or an external input) and the function at pins 9 and 25.
Refer to Table 6.
Command Register (CR)
Table 7 illustrates the command register. Bits CR0 (TxEN) and CR2
(RxEN) enable or disable the transmitter and receiver respectively.
A 0– to–1 transition of CR2 forces start bit search (async mode) or
hunt mode (sync mode) on the second RxC rising edge. Disabling
the receiver causes RxRDY to go High (inactive). If the transmitter
is disabled, it will complete the transmission of the character in the
transmit shift register (if any) prior to terminating operation. The TxD
output will then remain in the marking state (High) while TxRDY and
TxEMT will go High (inactive). If the receiver is disabled, it will
terminate operation immediately. Any character being assembled
will be neglected. A 0–to–1 transition of CR2 will initiate start bit
search (async) or hunt mode (sync).
Bits CR1 (DTR) and CR5 (RTS) control the DTR and RTS outputs.
Data at the outputs are the logical complement of the register data.
In asynchronous mode, setting CR3 will force and hold the TxD
output Low (spacing condition) at the end of the current transmitted
character. Normal operation resumes when CR3 is cleared. The
TxD line will go High for at least one bit time before beginning
transmission of the next character in the transmit data holding
register. In synchronous mode, setting CR3 causes the
transmission of the DLE register contents prior to sending the
character in the transmit data holding register. Since this is a one
time command, CR3 does not have to be reset by software. CR3
should be set when entering and exiting transparent mode and for
all DLE-non-DLE character sequences.
Setting CR4 causes the error flags in the status register (SR3, SR4,
and SR5) to be cleared; this is a one time command. There is no
internal latch for this bit.
When CR5 (RTS) is set, the RTS pin is forced Low. A 1–to–0
transition of CR5 will cause RTS to go High (inactive) one TxC time
after the last serial bit has been transmitted. If a 1–to–0 transition
of CR5 occurs while data is being transmitted, RTS will remain Low
(active) until both the THR and the transmit shift register are empty
and then go High (inactive) one TxC time later.
The EPCI can operate in one of four submodes within each major
mode (synchronous or asynchronous). The operational sub-mode is
determined by CR7 and CR6. CR7 – CR6 = 00 is the normal mode,
with the transmitter and receive operating independently in
accordance with the mode and status register instructions.
In asynchronous mode, CR7 – CR6 = 01 places the EPCI in the
automatic echo mode. Clocked, regenerated received data are
automatically directed to the TxD line while normal receiver
operation continues. The receiver must be enabled (CR2 = 1), but
the transmitter need not be enabled. CPU to receiver
communication continues normally, but the CPU to transmitter link is
disabled. Only the first character of a break condition is echoed.
The TxD output will go High until the next valid start is detected.
The following conditions are true while in automatic echo mode:
1. Data assembled by the receiver are automatically placed in the
transmit holding register and retransmitted by the transmitter on
the TxD output.
2. The transmitter is clocked by the receive clock.
3. TxRDY output = 1.
4. The TxEMT/DSCHG pin will reflect only the data set change
condition.
5. The TxEN command (CR0) is ignored.
In synchronous mode, CR7 – CR6 = 01 places the EPCI in the
automatic SYN/DLE stripping mode. The exact action taken
depends on the setting of bits MR17 and MR16:
1. In the non-transparent, single SYN mode (MR17 – MR16 = 10),
characters in the data stream matching SYN1 are not transferred
to the Receive Data Holding register (RHR).
2. In the non-transparent, double SYN mode (MR17 – MR16 = 00),
character in the data stream matching SYN1, or SYN2 if immedi-
ately preceded by SYN1, are not transferred the RHR.
3. In transparent mode (MR16 = 1), character in the data stream
matching DLE, or SYN1 if immediately preceded by DLE, are not
transferred to the RHR. However, only the first DLE of a DLE–
DLE pair is stripped.
Note that automatic stripping mode does not affect the setting of the
DLE detect and SYN detect status bits (SR3 and SR5).
Two diagnostic sub-modes can also be configured. In local
loopback mode (CR7 – CR6 = 10), the following loops are
connected internally:
1994 Apr 27
11

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