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PDF CHD408LVS Data sheet ( Hoja de datos )
| Número de pieza | CHD408LVS | |
| Descripción | 4M-Bit Low Power Asynchronous SRAM | |
| Fabricantes | MIRA | |
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CHD408LVS-55,70 CHD408LVW-55,70
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAM™
Rev 2.2 Jul’03
LOW-POWER ASYNCHRONOUS SRAM
DESCRIPTION
The CHD408L is a family of low voltage, low
power 4Mbit static RAMs organized as
512K-words by 8-bit, designed with Cascade’s
patent pending SuperT-SRAM™ technology,
fabricated with low-power 0.18µm process
technology.
The CHD408LVS is designed specifically for
low-power applications such as mobile cellular
phones, personal digital assistants and other
battery-operated products.
CHD408LVS -55,70 is packaged in sTSOP-I
packages, with normal and reverse lead-bending.
sTSOP-I packages are available in dimensions of
8x12mm and 8x20mm.
FEATURES
• Low power
- Low active and standby power for hand-held applications.
- Single power supply.
• High Performance
- 55ns or 70ns access time
• Compatibility
- 100% compatible with JEDEC asynchronous SRAM.
- No clocks, no refresh.
- No timing restrictions.
- No special power-up sequence requirement.
- Direct TTL compatibility for all inputs and outputs.
• Technology
- Designed with Cascade’s patent pending
SuperT-SRAM™ technology.
- Fabricated with low-power 0.18µm process
technology.
• Extended temperature range –40 ~ 85°C .
PART NAME TABLE & KEY SPEC SUMMARY
Power Supply
Part Name
2.7V ~ 3.6V
CHD408LVx-70
Max. Access
Time @ 2.7V
70ns
Standby Icc
Max @ 3.0V
85°C
35 µA
Active Icc
3.0V 10MHz
8mA
3.0V ~ 3.6V
CHD408LVx-55
55ns
35 µA
8mA
PART SELECTION TABLE
w Part Name
Package
Lead Bending
ww CHD408LVS-55,70
.D CHD408LVS-55,70-R
atCHD408LVW-55,70
aShCHD408LVW-55,70-R
8x12mm
STSOP-I
8x12m m
STSOP-I
8x20mm
STSOP-I
8x20mm
S TSOP-I
Normal
Reverse
Normal
Reverse
eet4U. Deutron Electronics Corporation
com8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
1
1 page  
CAPACITANCE
Parameter
CI Input Capacitance
CO Output Capacitance
Min Typ
CHD408LVS-55,70 CHD408LVW-55,70
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAM™
Rev 2.2 Jul’03
LOW-POWER ASYNCHRONOUS SRAM
Max Notes
8pF
8pF
AC ELECTRICAL CHARATERISTICS
(1) TEST CONDITIONS
Parameter
Value
VCC
Input pulse level
2.7-3.6V
VIH=2.4V, VIL=0.4V
Input rise and fall time
Reference level
Output loads
5ns
VOH=VOL=1.5V
30pF
Notes
Plus one TTL input load
1 TTL Load
DQ
Cload
including jig and scope
(2) READ CYCLE
Parameter
tCR
ta(A)
ta(S)
ta(OE)
tdis(S)
tdis(OE)
ten(S)
ten(OE)
tv(A)
Read cycle time (ns)
Address access time (ns)
Chip select access time (ns)
Output e nable access time (ns)
Output disable after /S (ns)
Output disable after /OE (ns)
Output enable after /S (ns)
Output enable after /OE (ns)
Data valid time after address
CHD408LVS-55(-R)
Min Max
55 -
- 55
- 55
- 25
- 15
- 15
5-
5-
10 -
CHD408LVS-70(-R)
Min Max
70 -
- 70
- 70
- 35
- 25
- 25
5-
5-
10 -
Deutron Electronics Corporation
8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
5
5 Page 
CHD408LVS-55,70 CHD408LVW-55,70
4M -BIT (512K-WORD BY 8-BIT) SuperT-SRAM™
Rev 2.2 Jul’03
LOW-POWER ASYNCHRONOUS SRAM
4M SuperT -SRAM™ CHD408LVx-55,70 Datashe et Revision History
Preliminary 0.1 2/21/02 WC
Rev 1.0
6/13/02 SC
Rev 1.1
Rev 2.0
Rev 2.1
Rev 2.2
½/03 SC
3/20/03 JG
7/11/03 WC
7/22/03 WC
Preliminary initial version
Added more detailed DC parameters and test conditions;
fixed some DC parameter numbers.
Added figure for output load
Updated A17/A18 assignment to be consistent with industry
convention.
Added -55 grade
Added 8x20mm TSOP-I package
Renamed LVS-70W to LVW-70, to be consistent with
naming convention.
- The information contained herein is subject to change without notice.
Deutron Electronics Corporation
8F, 68, SEC. 3, NAKING E. RD., TAIPEI 104, TAIWAN, R.O.C.
11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CHD408LVS.PDF ] | |
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