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Número de pieza | EBD52EC8AKFA-5 | |
Descripción | 512MB Unbuffered DDR SDRAM DIMM | |
Fabricantes | Elpida Memory | |
Logotipo | ||
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No Preview Available ! PRELIMINARY DATA SHEET
512MB Unbuffered DDR SDRAM DIMM
EBD52EC8AKFA-5 (64M words × 72 bits, 2 Ranks)
Description
The EBD52EC8AKFA is 64M words × 72 bits, 2 ranks
Double Data Rate (DDR) SDRAM unbuffered module,
mounting 18 pieces of 256M bits DDR SDRAM sealed
in TSOP package. Read and write operations are
performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2 bits
prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology. Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
• 184-pin socket type dual in line memory module
(DIMM)
PCB height: 31.75mm
Lead pitch: 1.27mm
• 2.5V power supply
• Data rate: 400Mbps (max.)
• 2.5 V (SSTL_2 compatible) I/O
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
• Data inputs and outputs are synchronized with DQS
• 4 internal banks for concurrent operation
(Component)
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
• Programmable burst length: 2, 4, 8
• Programmable /CAS latency (CL): 3
• Programmable output driver strength: normal/weak
• Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
• 2 variations of refresh
Auto refresh
Self refresh
Document No. E0356E30 (Ver. 3.0)
Date Published June 2003 (K) Japan
URL: http://www.elpida.com
Elpida Memory , Inc. 2003
1 page EBD52EC8AKFA-5
Serial PD Matrix
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
Total number of bytes in serial PD
device
0 0 0 0 1 0 0 0 08H
Memory type
0 0 0 0 0 1 1 1 07H
Number of row address
0 0 0 0 1 1 0 1 0DH
Number of column address
0 0 0 0 1 0 1 0 0AH
Number of DIMM ranks
0 0 0 0 0 0 1 0 02H
Module data width
0 1 0 0 1 0 0 0 48H
Module data width continuation
0 0 0 0 0 0 0 0 00H
Voltage interface level of this assembly 0 0 0 0 0 1 0 0 04H
DDR SDRAM cycle time, CL = 3
0 1 0 1 0 0 0 0 50H
SDRAM access from clock (tAC)
0 1 1 1 0 0 0 0 70H
DIMM configuration type
0 0 0 0 0 0 1 0 02H
Refresh rate/type
1 0 0 0 0 0 1 0 82H
Primary SDRAM width
0 0 0 0 1 0 0 0 08H
Error checking SDRAM width
0 0 0 0 1 0 0 0 08H
SDRAM device attributes:
Minimum clock delay back-to-back 0 0 0 0 0 0 0 1 01H
column access
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 1 0 0EH
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
SDRAM device attributes:
/CAS latency
0 0 0 1 1 1 0 0 1CH
SDRAM device attributes:
/CS latency
0 0 0 0 0 0 0 1 01H
SDRAM device attributes:
/WE latency
0 0 0 0 0 0 1 0 02H
21 SDRAM module attributes
0 0 1 0 0 0 0 0 20H
22 SDRAM device attributes: General 1 1 0 0 0 0 0 0 C0H
23 Minimum clock cycle time at CL = 2.5 0 1 1 0 0 0 0 0 60H
24
Maximum data access time (tAC) from
clock at CL = 2.5
0
1
1
1
0
0
0
0
70H
25 Minimum clock cycle time at CL = 2 0 1 1 1 0 1 0 1 75H
26
Maximum data access time (tAC) from
clock at CL = 2
0
1
1
1
0
1
0
1
75H
27
Minimum row precharge time (tRP)
-5B
0
0
1
1
1
1
0
0
3CH
-5C 0 1 0 0 1 0 0 0 48H
28
Minimum row active to row active
delay (tRRD)
0 0 1 0 1 0 0 0 28H
29
Minimum /RAS to /CAS delay (tRCD)
-5B
0
0
1
1
1
1
0
0
3CH
-5C 0 1 0 0 1 0 0 0 48H
30
Minimum active to precharge time
(tRAS)
0 0 1 0 1 0 0 0 28H
31 Module rank density
0 1 0 0 0 0 0 0 40H
Comments
128 bytes
256 bytes
DDR SDRAM
13
10
2
72 bits
0
SSTL2
5.0ns*1
0.7ns*1
ECC
7.8µs
×8
×8
1 CLK
2, 4, 8
4
2, 2.5, 3
0
1
Differential
Clock
VDD ± 0.2V
6.0ns*1
0.7ns*1
0.75ns*1
0.75ns*1
15ns
18ns
10ns
15ns
18ns
40ns
256M bytes
Preliminary Data Sheet E0356E30 (Ver. 3.0)
5
5 Page EBD52EC8AKFA-5
DC Characteristics 1 (TA = 0 to +70°C, VDD = 2.6V ± 0.1V, VSS = 0V)
Parameter
Symbol
Grade
max.
Unit Test condition
Notes
Operating current (ACTV-PRE)
Operating current
(ACTV-READ-PRE)
IDD0
IDD1
-5B 1530
-5C 1440
-5B 1800
-5C 1710
mA
CKE ≥ VIH,
tRC = tRC (min.)
1, 2, 9
CKE ≥ VIH, BL = 2,
mA CL = 3,
1, 2, 5
tRC = tRC (min.)
Idle power down standby current IDD2P
54
mA CKE ≤ VIL
4
Floating idle
Standby current
IDD2F
540 mA CKE ≥ VIH, /CS ≥ VIH 4, 5
Quiet idle
Standby current
IDD2Q
450
mA
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
4, 10
Active power down
standby current
IDD3P
360
mA CKE ≤ VIL
3
Active standby current
IDD3N
1080
mA
CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)
3, 5, 6
Operating current
(Burst read operation)
IDD4R
2340
mA
CKE ≥ VIH, BL = 2,
CL = 3
1, 2, 5, 6
Operating current
(Burst write operation)
IDD4W
2430
mA
CKE ≥ VIH, BL = 2,
CL = 3
1, 2, 5, 6
Auto refresh current
IDD5
3060
mA
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
Self refresh current
IDD6
54
mA
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
Operating current
(4 banks interleaving)
IDD7A
3420
mA BL = 4
5, 6, 7
Notes. 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one cycle.
6. DQ, DM and DQS transition twice per one cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once per one every two clock cycles.
10. Command/Address stable at ≥ VIH or ≤ VIL.
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.6V ± 0.1V, VSS = 0V)
Parameter
Symbol
min.
max.
Unit Test condition
Input leakage current
ILI
–36
Output leakage current
ILO
–10
Output high current IOH –15.2
Output low current IOL 15.2
Note: 1. DDR SDRAM component specification.
36
10
—
—
µA VDD ≥ VIN ≥ VSS
µA VDD ≥ VOUT ≥ VSS
mA VOUT = 1.95V
mA VOUT = 0.35V
Notes
1
1
Preliminary Data Sheet E0356E30 (Ver. 3.0)
11
11 Page |
Páginas | Total 19 Páginas | |
PDF Descargar | [ Datasheet EBD52EC8AKFA-5.PDF ] |
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