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PDF DPS128M8xxx Data sheet ( Hoja de datos )
| Número de pieza | DPS128M8xxx | |
| Descripción | 128kx8 High Speed CMOS SRAM | |
| Fabricantes | Dense-Pac Microsystems | |
| Logotipo |  |
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1 Megabit High Speed CMOS SRAM
DPS128M8CnY/BnY, DPS128X8CA3/BA3
DESCRIPTION:
The DPS128M8CnY/BnY, DPS128X8CA3/BA3 High Speed SRAM
devices are a revolutionary new memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC).
Available in straight leaded, ‘’J’’ leaded or gullwing leaded packages,
or mounted on a 50-pin PGA co-fired ceramic substrate. These devices
pack 1-Megabits of low-power CMOS static RAM in an area as small
as 0.463 in2, while maintaining a total height as low as 0.082 inches.
The SLCC devices contain an individual 128K x 8 SRAMs, each
packaged in a hermetically sealed SLCC, making the modules suitable
for commercial, industrial and military applications.
The DPS128M8BnY/DPS128X8BA3 has one active low Chip Enable
(CE) while the DPS128M8CnY/DPS128X8CA3 has an active low Chip
Enable (CE) and an active high Select Line (SEL).
By using SLCCs, the ‘’Stack’’ family of modules offer a higher board
density of memory than available with conventional through-hole,
surface mount or hybrid techniques.
SLCC
‘’I’’ Leaded
SLCC
FEATURES:
• Organization Available: 128Kx8
• Access Times: 20*, 25, 30, 35, 45ns
• Fully Static Operation - No clock or refresh required
• Single +5V Power Supply, ±10% Tolerance
• TTL Compatible
• Common Data Inputs and Outputs
• Low Data Retention Voltage: 2.0V min.
• Packages Available:
‘’J’’ Leaded
SLCC
48 - Pin SLCC
48 - Pin Straight Leaded SLCC
48 - Pin ‘’J’’ Leaded SLCC
48 - Pin Gullwing Leaded SLCC
50 - Pin PGA Dense-Stack
w * Commercial only.
ww. Dense-Stack
Gullwing
Leaded SLCC
DataSheet430A097-31
U.comREV. D
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
1 page  
Dense-Pac Microsystems, Inc.
DPS128M8CnY/BnY, DPS128X8CA3/BA3
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges
No. Symbol
Parameter
20ns*
Min. Max.
25ns
Min. Max.
30ns
Min. Max.
35ns
Min. Max.
45ns
Min. Max.
Unit
1 tRC Read Cycle Time
20 25 30 35 45 ns
2 tAA Address Access Time
20 25 30 35 45 ns
3 tCO1 CE to Output Valid
20 25 30 35 45 ns
4 tCO2 SEL to Output Valid
20 25 30 35 45 ns
5 tOE Output Enable to Output Valid
8 10 15 20 25 ns
6 tLZ1 CE to Output in LOW-Z 4, 5
3 3 3 3 3 ns
7 tLZ2 SEL to Output in LOW-Z 4, 5
3 3 3 3 3 ns
8 tOLZ Output Enable to Output in LOW-Z 4, 5 0 0 0 0 0 ns
9 tHZ1 CE to Output in HIGH-Z 4, 5
10 12 15 20 25 ns
10 tHZ2 SEL to Output in HIGH-Z 4, 5
10 12 15 20 25 ns
11 tOHZ Output Enable to Output in HIGH-Z 4, 5 8 10 15 20 25 ns
12 tOH Output Hold from Address Change
3
3
3
3
3 ns
* Available in Commercial Only.
NOTE: tCO2, tLZ2 and tHZ2 apply to DPS128M8CnY/DPS128X8CA3 version only.
READ CYCLE
ADDRESS
CE
SEL
OE
DATA I/O
NOTE: SEL, tCO2, tLZ2 and tHZ2 apply to DPS128M8CnY/DPS128X8CA3 version only.
Data Valid
30A097-31
REV. D
WAVEFORM KEY
Transition from
HIGH to LOW
Transition from
LOW to HIGH
Data Undefined
or Don’t Care
5
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