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Número de pieza LH75411
Descripción (LH75400/01/10/11) System-on-Chip Preliminary User Guide
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No Preview Available ! LH75411 Hoja de datos, Descripción, Manual

LH75400/01/10/11
System-on-Chip
Preliminary User’s Guide
12/8/03

1 page




LH75411 pdf
Table of Contents
LH75400/01/10/11 (Preliminary) User’s Guide
Chapter 4 – LH75400 SoC
4.1 LH75400 Features............................................................................................ 4-1
4.2 LH75400 Block Diagram .................................................................................. 4-2
4.3 LH75400 Applications ...................................................................................... 4-3
4.4 LH75400 Pin Diagram ...................................................................................... 4-4
4.5 LH75400 Numerical Pin Listing ........................................................................ 4-5
4.6 LH75400 Signal Descriptions ........................................................................... 4-9
Chapter 5 – LH75410 SoC
5.1 LH75410 Features............................................................................................ 5-1
5.2 LH75410 Block Diagram .................................................................................. 5-2
5.3 LH75410 Applications ...................................................................................... 5-3
5.4 LH75410 Pin Diagram ...................................................................................... 5-4
5.5 LH75410 Numerical Pin Listing ........................................................................ 5-5
5.6 LH75410 Signal Descriptions ........................................................................... 5-9
Chapter 6 – Memory Interface Architecture
Chapter 7 – Static Memory Controller
7.1 SMC Features .................................................................................................. 7-1
7.2 SMC Theory of Operation ................................................................................ 7-2
7.2.1 SMC Write Process ................................................................................... 7-2
7.2.2 SMC Read Process ................................................................................... 7-4
7.2.3 SMC Burst Mode Read Process ............................................................... 7-4
7.2.4 External Memory Bus Cycle ...................................................................... 7-8
7.2.5 External Bus Read/Write Operations ........................................................ 7-9
7.2.6 SMC Memory Connection Diagram......................................................... 7-11
7.3 SMC Programmer’s Model ............................................................................. 7-12
7.3.1 SMC Register Summary.......................................................................... 7-12
7.3.2 SMC Register Definitions ........................................................................ 7-13
7.3.2.1 Configuration Register for Memory Bank 0 ...................................... 7-13
7.3.2.2 Configuration Register for Memory Bank 1 ...................................... 7-15
7.3.2.3 Configuration Register for Memory Bank 2 ...................................... 7-17
7.3.2.4 Configuration Register for Memory Bank 3 ...................................... 7-19
7.3.3 SMC Default Memory Widths .................................................................. 7-21
Chapter 8 – Static Random Access Memory Controller
Chapter 9 – Reset, Clock, and Power Controller
9.1 RCPC Features ................................................................................................ 9-2
9.2 RCPC Theory of Operation .............................................................................. 9-2
9.2.1 Reset Generation ...................................................................................... 9-3
9.2.2 Clock Generation....................................................................................... 9-4
9.2.3 RCPC Power Modes ................................................................................. 9-4
9.2.3.1 Active Mode........................................................................................ 9-5
9.2.3.2 Standby Mode .................................................................................... 9-5
9.2.3.3 Sleep Mode ........................................................................................ 9-5
9.2.3.4 Stop1 Mode ........................................................................................ 9-5
9.2.3.5 Stop2 Mode ........................................................................................ 9-5
9.3 RCPC Programmer’s Model............................................................................. 9-6
iv 10/29/03

5 Page





LH75411 arduino
Table of Contents
LH75400/01/10/11 (Preliminary) User’s Guide
18.5.3 SSP Interrupts ..................................................................................... 18-19
18.5.3.1 Receive Interrupt .......................................................................... 18-19
18.5.3.2 Transmit Interrupt ......................................................................... 18-19
18.5.3.3 Receive Overrun Interrupt ............................................................ 18-19
18.5.3.4 Receive Timeout Interrupt ............................................................ 18-20
18.5.3.5 SSPINTR ...................................................................................... 18-20
Chapter 19 – UART0 and UART1
19.1 UART0 and UART1 Features....................................................................... 19-2
19.2 UART0 and UART1 Theory of Operation..................................................... 19-2
19.2.1 UART0 and UART1 Receiver Data Frame............................................ 19-2
19.2.2 Status Conditions .................................................................................. 19-3
19.2.3 On-Chip DMA Capabilities .................................................................... 19-4
19.2.4 Programming Control Registers ............................................................ 19-4
19.3 UART0 and UART1 Programmer’s Model ................................................... 19-5
19.3.0.1 UART0 and UART1 Register Summary ........................................ 19-5
19.3.1 UART0 and UART1 Register Definitions............................................... 19-6
19.3.1.1 Data Register.................................................................................. 19-6
19.3.1.2 Receive Status/Error Clear Register.............................................. 19-8
19.3.1.3 Flag Register ................................................................................ 19-10
19.3.1.4 UART Line Control Register ......................................................... 19-11
19.3.1.5 Integer Baud Rate Divisor Register .............................................. 19-12
19.3.1.6 Fractional Baud Rate Divisor Register ......................................... 19-13
19.3.1.7 Calculating the Divisor Value........................................................ 19-14
19.3.1.8 Typical Bit Rates and Their Corresponding Divisor...................... 19-14
19.3.1.9 Line Control Register.................................................................... 19-15
19.3.1.10 UART Control Register............................................................... 19-17
19.3.1.11 Interrupt FIFO Level Select Register .......................................... 19-18
19.3.1.12 Interrupt Mask Set/Clear Register .............................................. 19-19
19.3.1.13 Raw Interrupt Status Register .................................................... 19-21
19.3.1.14 Masked Interrupt Status Register ............................................... 19-22
19.3.1.15 ICR ............................................................................................. 19-23
19.3.1.16 DMACTRL .................................................................................. 19-24
19.3.2 UART0 and UART1 Interrupts............................................................. 19-25
19.3.2.1 UARTRXINTR .............................................................................. 19-25
19.3.2.2 UARTTXINTR............................................................................... 19-25
19.3.2.3 UARTINTR ................................................................................... 19-25
Chapter 20 – UART2
20.1 UART2 Features .......................................................................................... 20-2
20.2 UART2 Theory of Operation......................................................................... 20-2
20.2.1 UART Receiver Data Frame ................................................................. 20-3
20.2.2 Status Conditions .................................................................................. 20-5
20.2.3 Disabling the Loading of Incoming Characters...................................... 20-5
20.2.4 Baud Rate Generators .......................................................................... 20-6
20.3 UART2 Programmer’s Model ....................................................................... 20-7
20.3.1 UART2 Register Summary .................................................................... 20-7
20.3.1.1 Register Bank 0 .............................................................................. 20-7
x 10/29/03

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