PDF KM718V987 Data sheet ( Hoja de datos )

Número de pieza	KM718V987
Descripción	(KM736V887 / KM718V987) 256Kx36 & 512Kx18 Synchronous SRAM
Fabricantes	Samsung semiconductor
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No Preview Available ! KM736V887 KM718V987 256Kx36 & 512Kx18 Synchronous SRAM Document Title 256Kx36 & 512Kx18-Bit Synchronous Burst SRAM Revision History Rev. No. 0.0 History Initial draft 0.1 Change DC Characteristics. ISB value from 60mA to 90mA at -8 ISB value from 50mA to 80mA at -9 ISB value from 40mA to 70mA at -10 ISB1 value from 10mA to 30mA ISB2 value from 10mA to 30mA 0.2 1. Changed tCD from 8.0ns to 8.5ns at -8 2. Changed tCYC from 13.0ns to 12.0ns at -10 3. Changed DC condition at Icc and parameters ICC ; from 300mA to 350mA at -8, from 260mA to 300mA at -9, from 220mA to 260mA at -10, ISB ; from 90mA to 130mA at -8, from 80mA to 120mA at -9, from 70mA to 110mA at -10, 0.3 1. ADD 119BGA(7x17 Ball Grid Array Package) . 2. ADD x32 organization. 0.4 Add VDDQ Supply voltage( 2.5V ) 0.5 Changed VOL Max value from 0.2V to 0.4V at 2.5V I/O. 1.0 1. Final Spec Release. 2. Remove x32 organization. 2.0 1. Remove VDDQ supply voltage(2.5V) 3.0 1. Changed ICC from 350mA to 330mA at -8. 2. Add bin -7. (tCD 7.5ns). 4.0 1. Add VDDQ supply voltage(2.5V) Draft Date April. 10 . 1998 Aug. 31. 1998 Remark Preliminary Preliminary Sep. 09. 1998 Preliminary Oct. 15. 1998 Preliminary Dec. 10. 1998 Dec. 23. 1998 Jan. 29. 1999 Preliminary Preliminary Final Feb. 25. 1999 Mar. 30. 1999 Final Final May. 13. 1999 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques- tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. - 1 - May 1999 Rev 4.0 1 page KM736V887 KM718V987 256Kx36 & 512Kx18 Synchronous SRAM 119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW) KM736V887(256Kx36) 123456 A VDDQ A A ADSP A A B NC CS2 A ADSC A A C NC A A VDD A A D DQc DQPc VSS NC VSS DQPb E DQc DQc VSS CS1 VSS DQb F VDDQ DQc VSS OE VSS DQb G DQc DQc WEc ADV WEb DQb H DQc DQc VSS GW VSS DQb J VDDQ VDD NC VDD NC VDD K DQd DQd VSS CLK VSS DQa L DQd DQd WEd NC WEa DQa M VDDQ DQd VSS BW VSS DQa N DQd DQd VSS A1* VSS DQa P DQd DQPd VSS A0* VSS DQPa R NC A LBO VDD NC A T NC NC A A A NC U VDDQ NC NC NC NC NC Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ PIN NAME SYMBOL A A0, A1 ADV ADSP ADSC CLK CS1 CS2 WEx (x=a,b,c,d) OE GW BW ZZ LBO PIN NAME Address Inputs Burst Count Address Burst Address Advance Address Status Processor Address Status Controller Clock Chip Select Chip Select Byte Write Inputs Output Enable Global Write Enable Byte Write Enable Power Down Input Burst Mode Control SYMBOL VDD VSS N.C. DQa DQb DQc DQd DQPa~Pd VDDQ PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outpus Output Power Supply (2.5V or 3.3V) - 5 - May 1999 Rev 4.0 5 Page KM736V887 KM718V987 Output Load(A) Dout Zo=50Ω 256Kx36 & 512Kx18 Synchronous SRAM RL=50Ω VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) Dout +3.3V for 3.3V I/O /+2.5V for 2.5V I/O 319Ω / 1667Ω 353Ω / 1538Ω 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C) PARAMETER -7 SYMBOL MIN MAX -8 MIN MAX -9 MIN MAX -10 UNIT MIN MAX Cycle Time tCYC 8.5 - 10 - 12 - 12 - ns Clock Access Time tCD - 7.5 - 8.5 - 9.0 - 10 ns Output Enable to Data Valid tOE - 3.5 - 3.5 - 3.5 - 3.5 ns Clock High to Output Low-Z tLZC 2.5 - 2.5 - 2.5 - 2.5 - ns Output Hold from Clock High tOH 2.5 - 2.5 - 2.5 - 2.5 - ns Output Enable Low to Output Low-Z tLZOE 0 - 0 - 0 - 0 - ns Output Enable High to Output High-Z tHZOE - 3.5 - 3.5 - 3.5 - 4.0 ns Clock High to Output High-Z tHZC - 4.0 - 5.0 - 5.0 - 6.0 ns Clock High Pulse Width tCH 2.5 - 3.0 - 3.0 - 3.0 - ns Clock Low Pulse Width tCL 2.5 - 3.0 - 3.0 - 3.0 - ns Address Setup to Clock High tAS 2.0 - 2.0 - 2.0 - 2.0 - ns Address Status Setup to Clock High tSS 2.0 - 2.0 - 2.0 - 2.0 - ns Data Setup to Clock High tDS 2.0 - 2.0 - 2.0 - 2.0 - ns Write Setup to Clock High (GW, BW, WEX) tWS 2.0 - 2.0 - 2.0 - 2.0 - ns Address Advance Setup to Clock High tADVS 2.0 - 2.0 - 2.0 - 2.0 - ns Chip Select Setup to Clock High tCSS 2.0 - 2.0 - 2.0 - 2.0 - ns Address Hold from Clock High tAH 0.5 - 0.5 - 0.5 - 0.5 - ns Address Status Hold from Clock High tSH 0.5 - 0.5 - 0.5 - 0.5 - ns Data Hold from Clock High tDH 0.5 - 0.5 - 0.5 - 0.5 - ns Write Hold from Clock High (GW, BW, WEX) tWH 0.5 - 0.5 - 0.5 - 0.5 - ns Address Advance Hold from Clock High tADVH 0.5 - 0.5 - 0.5 - 0.5 - ns Chip Select Hold from Clock High tCSH 0.5 - 0.5 - 0.5 - 0.5 - ns ZZ High to Power Down tPDS 2 - 2 - 2 - 2 - cycle ZZ Low to Power Up tPUS 2 - 2 - 2 - 2 - cycle Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled. 3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state. - 11 - May 1999 Rev 4.0 11 Page

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