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PDF ICS9250-18 Data sheet ( Hoja de datos )
| Número de pieza | ICS9250-18 | |
| Descripción | Frequency Generator & Integrated Buffers for Celeron & PII/III | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS9250-18 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS9250-18
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
BX, Appollo Pro 133 type of chip set.
Output Features:
• 3 - CPUs @2.5V, up to 166MHz.
• 17 - SDRAM @ 3.3V, up to 166MHz.
• 7 - PCI @3.3V
• 2 - IOAPIC @ 2.5V
• 1 - 48MHz, @3.3V fixed.
• 1 - 24MHz @ 3.3V
• 2 - REF @3.3V, 14.318MHz.
Features:
• Up to 166MHz frequency support
• Support power management: CPU, PCI, stop and Power
down Mode form I2C programming.
• Spread spectrum for EMI control (± 0.25% center spread)
• Uses external 14.318MHz crystal
Key Specifications:
• CPU – CPU: <175ps
• CPU – PCI: 1 - 4ns
• PCI – PCI: <500ps
• SDRAM - SDRAM: <250ps
VDDREF
*FS2/REF1
*PCI_STOP#/REF0
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
*FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
PCICLK5
BUFFERIN
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
{I 2 C
SDATA
SCLK
Pin Configuration
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 43
15 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
VDDLIOAPIC
IOAPIC0
IOAPIC_F
GND
CPUCLK_F
CPUCLK1
VDDLCPU
CPUCLK2
GND
CPU_STOP#
SDRAM_F
VDDSDR
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM12
SDRAM13
VDD48
24MHz/FS0*
48MHz/FSI*1
56-Pin SSOP
Block Diagram
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
** Internal Pull-down resistor of 240K to GND on indicated inputs.
1. This output is double strength.
Functionality
FS3 FS2 FS1 FS0
0000
000 1
00 10
00 11
0 100
0 10 1
0 110
0 111
10 0 0
100 1
10 10
10 11
1 10 0
110 1
1 1 10
1111
CPU
(MHz)
80.00
75.00
83.31
66.9
103.00
112.01
68.01
100.7
120.00
114.99
109.99
105.00
140.00
150.00
124.00
133.9
PCICLK
(MHz)
40.00
37.50
41.65
33.45
34.33
37.34
34.01
33.57
40.00
38.33
36.66
35.00
35.00
37.50
31.00
33.25
9250-18 Rev B 9/23/99
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS9250-18
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit
2,7, 6:4
Bit 3
Bit 1
Bit 0
Description
Bit2 Bit7 Bit6 Bit5
Bit4
CPUCLK
MHz
PCICLK
MHz
0 0 0 0 0 80.00
40.00
0 0 0 0 1 75.00
37.50
0001 0
83.31
41.65
0 00 1
1
66.9
33.45
0 0 1 0 0 103.00 34.33
0 0 10
1 112.01
37.34
0011 0
68.01
34.01
0 0 1 1 1 100.7
33.57
0 1 0 0 0 120.00 40.00
0 100
1 114.99
38.33
0 10 1 0
109.99
36.66
0 10 1
1 105.00
35.00
0 1 1 0 0 140.00 35.00
0 110
1 150.00
37.50
0 111 0
124.00
31.00
0 1 1 1 1 133.9
33.25
1 0 0 0 0 135.00 33.75
1000
1 129.99
32.50
1001 0
126.00
31.50
100 1
1 118.00
39.33
1 0 1 0 0 115.98 38.66
1 0 1 0 1 95.00
31.67
1011 0
90.00
30.00
1 0 1 1 1 85.01
28.34
1 1 0 0 0 166.00 41.50
1 100
1 160.01
40.00
1 10 1 0
154.99
38.75
1 10 1
1 147.95
36.99
1 1 1 0 0 145.98 36.50
1 110
1 143.98
35.99
1111 0
141.99
35.50
1 1 1 1 1 138.01 34.50
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2, 7:4
0 - Normal
1 - Spread Spectrum Enabled ±0.25% (Center Spread)
0 - Running
1- Tristate all outputs
Note 1. Default at Power-up will be for latched logic inputs to define frequency as
displayed by Bit 3.
Note: PWD = Power-Up Default
PWD
XXXX
Note1
0
1
0
Third party brands and names are the property of their respective owners.
5
5 Page 
ICS9250-18
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Output High Voltage
VOH2B IOH = -12.0 mA
Output Low Voltage
VOL2B IOL = 12 mA
Output High Current
IOH2B
VOH = 1.7 V
Output Low Current
Rise Time
Fall Time
Duty Cycle
Skew group1: 1,2 and 1,F
Skew group2: 2, F
Jitter, One Sigma
Jitter, Absolute
Jitter, Cycle-to-cycle
IOL2B
tr2B1
tf2B1
dt2B1
tsk2B1
tsk2B1
tj1σ2B1
tjabs2B1
tjcyc-cyc2B1
VOL = 0.7 V
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
VT = 1.25 V
1Guaranteed by design, not 100% tested in production.
2
19
0.4
0.4
45
-250
TYP MAX UNITS
2.3 V
0.2 0.4 V
-41 -19 mA
37 mA
1.6 ns
1 1.6 ns
51 55.5 %
120 175 ps
254 ps
120 250 ps
100 +250 ps
150 250 ps
Electrical Characteristics - 48MHz, 24MHz,REF0
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Jitter1
Jitter1
VOH5
VOL5
IOH5
IOL5
tr5
tf5
dt5
tj1s5
tjabs5
IOH = -14 mA
IOL = 6.0 mA
VOH = 2.0 V
VOL = 0.8 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V, 24, 48MHz
VT = 1.5 V, REF0
2.4 2.9
V
0.25 0.4
V
-42 -20 mA
10 18
mA
1.1 2.5 ns
1 2.5 ns
45 50 55 %
100 250 ps
250 800 ps
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ICS9250-18.PDF ] | |
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