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Número de pieza | ICS9250-29 | |
Descripción | Frequency Generator & Integrated Buffers for Celeron & PII/III | |
Fabricantes | Integrated Circuit Systems | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de ICS9250-29 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
No Preview Available ! Integrated
Circuit
Systems, Inc.
ICS9250-29
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
Solano type chipset.
Output Features:
• 2 CPU (2.5V) (up to 133MHz achievable through I2C)
• 13 SDRAM (3.3V) (up to 133MHz achievable
through I2C)
• 5 PCI (3.3 V) @33.3MHz
• 1 IOAPIC (2.5V) @ 33.3 MHz
• 3 Hublink clocks (3.3 V) @ 66.6 MHz
• 2 (3.3V) @ 48 MHz (Non spread spectrum)
• 1 REF (3.3V) @ 14.318 MHz
Features:
• Supports spread spectrum modulation,
0 to -0.5% down spread.
• I2C support for power management
• Efficient power management scheme through PD#
• Uses external 14.138 MHz crystal
• Alternate frequency selections available through I2C
control.
Pin Configuration
IOAPIC
VDDL
GNDL
*FS1/REF
VDDR
X1
X2
GNDR
VDD3
3V66-0
3V66-1
3V66-2
GND3
PCICLK0
PCICLK1
PCICLK2
VDD2
GND2
PCICLK3
PCICLK4
FS0
GNDA
VDDA
SCLK
SDATA
GNDF
VDDF
48MHz_0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 GNDL
55 VDDL
54 CPUCLK0
53 CPUCLK1
52 GND1
51 SDRAM0
50 SDRAM1
49 VDD1
48 GND1
47 SDRAM2
46 SDRAM3
45 SDRAM4
44 SDRAM5
43 VDD1
42 GND1
41 SDRAM6
40 SDRAM7
39 SDRAM8
38 SDRAM9
37 VDD1
36 GND1
35 SDRAM10
34 SDRAM11
33 VDD1
32 GND1
31 SDRAM12
30 TRISTATE#/PD#**
29 48MHz_1
56-Pin 300mil SSOP
* This input has a 50K9 pull-down to GND.
** This input has a 50K9pull-up to VDD
Block Diagram
X1 XTAL
X2 OSC
PLL1
Spread
Spectrum
/2 /3
FS(1:0)
PD#
TRISTATE#
SDATA
SCLK
Control
Logic
Config
Reg
PLL2
/2
/2
REF
VDDL
2 CPU66/100/133 [1:0]
3V66 [2:0]
3
SDRAM [12:0]
13
PCICLK [4:0]
5
IOAPIC
VDDL
2 48MHz [1:0]
Functionality
Tristate#
0
0
1
1
1
1
FS0
0
1
0
1
0
1
FS1
CPU
MHz
SDRAM
MHz
X Tristate Tristate
X Test
Test
0 66MHz 100MHz
0 100MHz 100MHz
1 133MHz 133MHz
1 133MHz 100MHz
Power Groups
VDDA, GNDA = CPU, PLL (analog)
VDDF, GNDF = Fixed PLL, 48M (analog/digital)
VDDR, GNDR = REF, X1, X2 (analog/digital)
VDD3, GND3 = 3V66 (digital)
VDD2, GND2 = PCI (digital)
VDD1, GND1 = SDRAM (digital)
VDDL, GNDL = IOAPIC, CPU (digital)
9250-29 Rev A 02/01/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
1 page ICS9250-29
Truth Table
Tristate FS0 FS1 CPU
SDRAM 3V66
PCI 48MHz
REF IOAPIC
0
0 X Tristate
Tristate
Tristate Tristate
Tristate
Tristate
Tristate
0
1 X TCLK/2 TCLK/2 TCLK/3 TCLK/6 TCLK/2
TCLK
TCLK/6
1 0 0 66.6 MHz 100 MHz 66.6 MHz 33.3 MHz 48 MHz 14.318 MHz 33.3 MHz
1 1 0 100 MHz 100 MHz 66.6 MHz 33.3 MHz 48 MHz 14.318 MHz 33.3 MHz
1 0 1 133 MHz 133 MHz 66.6 MHz 33.3 MHz 48 MHz 14.318 MHz 33.3 MHz
1 1 1 133 MHz 100 MHz 66.6 MHz 33.3 MHz 48 MHz 14.318 MHz 33.3 MHz
Byte 0: Control Register
(1 = enable, 0 = disable)
Bit Pin#
Name
PWD Description
Bit 7 - (Reserved ID)
0 (Active / Inactive )
Bit 6 - (Reserved ID)
0 (Active / Inactive )
Bit 5 - (Reserved ID)
0 (Active / Inactive )
Bit 4 - (Reserved ID)
1 (Active / Inactive )
Bit 3 - Spread Spectrum 0 (1=On / 0=Off )
Bit 2 29 48MHz_1
1 (Active / Inactive )
Bit 1 28 48MHz_0
1 (Active / Inactive )
Bit 0 - (Reserved ID)
0 (Active / Inactive )
Note:
Reserved ID bits must be written with "0"
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit Pin#
Name
Bit 7 40 SDRAM7
Bit 6 41 SDRAM6
Bit 5 44 SDRAM5
Bit 4 45 SDRAM4
Bit 3 46 SDRAM3
Bit 2 47 SDRAM2
Bit 1 50 SDRAM1
Bit 0 51 SDRAM0
PWD Description
1 (Active / Inactive )
1 (Active / Inactive )
1 (Active / Inactive )
1 (Active / Inactive )
1 (Active / Inactive )
1 (Active / Inactive )
1 (Active / Inactive )
1 (Active / Inactive )
5
5 Page ICS9250-29
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN
Output Impedance
RDSP11 VO = VDD*(0.5)
Output Impedance
RDSN11 VO = VDD*(0.5)
Output High Voltage VOH1 IOH = -1 mA
Output Low Voltage
VOL1 IOL = 1 mA
Output High Current
IOH1 VOH@MIN = 1.0 V, VOH@MAX= 3.135 V
Output Low Current
IOL1 VOL@MIN= 1.95 V, VOL@MAX= 0.4
Rise Time
tr11 VOL = 0.4 V, VOH = 2.4 V
Fall Time
tf11 VOH = 2.4 V, VOL = 0.4 V
Duty Cycle
dt11 VT = 1.5 V
Skew
Jitter
tsk11
tjcyc-cyc1
VT = 1.5 V
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
12
12
2.4
-33
30
0.5
0.5
45
TYP
1.43
1.63
51.9
MAX UNITS
55 Ω
55 Ω
V
0.4 V
-33 mA
38 mA
2 ns
2 ns
55 %
500 ps
500 ps
Electrical Characteristics - REF, 48MHz_0
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%, CL = 10 -20 pF (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
Fall Time
Duty Cycle
Jitter
RDSP51
RDSN51
VOH5
VOL5
IOH5
IOL5
tr51
tf51
dt51
tjcyc-cyc1
tjcyc-cyc1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = 1 mA
IOL = -1 mA
VOH@MIN=1 V, VOH@MAX= 3.135 V
VOL@MIN=1.95 V, VOL@MIN=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V; Fixed Clocks
VT = 1.5 V; Ref Clocks
20
20
2.4
-29
29
1 1.53
1 1.76
45 53.6
1Guarenteed by design, not 100% tested in production.
MAX UNITS
60 Ω
60 Ω
V
0.4 V
-23 mA
27 mA
4 ns
4 ns
55 %
500 ps
1000 ps
11
11 Page |
Páginas | Total 15 Páginas | |
PDF Descargar | [ Datasheet ICS9250-29.PDF ] |
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