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PDF ICS9250-32 Data sheet ( Hoja de datos )
| Número de pieza | ICS9250-32 | |
| Descripción | Frequency Generator & Integrated Buffers for PII/III | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS9250-32
Frequency Generator & Integrated Buffers for PII/III™
Recommended Application:
Timna Style Chipset
Output Features:
• 3 - CPUs @ 2.5V
• 8 - PCI @ 3.3V
• 2 - IOAPIC @ 2.5V
• 1 - MREF @ 2.5V, DRCG memory reference clock
• 9 - SDRAM @ 3.3V including one free running
• 1 - 2V48M @ 2.5V fixed (DOT)
• 1 - 3V48M @ 3.3V fixed (USB)
• 2 - REF @ 3.3V, 14.318MHz.
Features:
• Support power management: CPU, PCI, SDRAM stop
from I2C programming.
• Spread spectrum for EMI control (0 to -0.5%)
• Uses external 14.318MHz crystal
Key Specifications:
• CPU Output Jitter (Cyc-Cyc): <175ps
• IOAPIC Output Jitter (Cyc-Cyc): <500ps
• MREF Output Jitter (Cyc-Cyc): <250ps
• 2V48M Output Jitter (Cyc-Cyc): <250ps
• 3V48M Output Jitter (Cyc-Cyc): <500ps
• CPU - CPU: < 175ps
• SDRAM - SDRAM < 250ps
• PCI - PCI: < 500ps
• IOAPIC - IOAPIC: < 250ps
• BUFFER_IN to SDRAM prop delay: 5.5 to 7.5ns
Block Diagram
PLL2
X1
X2
BUF_IN
CPU_EN#
SDATA
SCLK
FS (1:0)
XTAL
OSC
PLL1
Spread
Spectrum
Control
Logic
Config.
Reg.
CPU
DIVDER
SDRAM
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
3V66
DIVDER
3V48M
2V48M
REF (1:0)
2
CPUCLK (2:0)
3
SDRAM (7:0)
8
SDRAM_F
IOAPIC (1:0)
2
PCICLK (7:0)
8
MREF66
9250-32 Rev B 9/7/00
Third party brands and names are the property of their respective owners.
Pin Configuration
2V48M
3V48M
VDD48
GND48
X1
X2
GND
*(CPU2_EN#)REF0
REF1
VDD
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK5
VDDPCI
GNDPCI
PCICLK6
PCICLK7
SCLK
VDDA
GNDA
SDATA
BUF_IN
*FS0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VDDLIOAPIC
55 IOAPIC0
54 IOAPIC1
53 GNDLIOAPIC
52 VDDLCPU
51 CPUCLK0
50 CPUCLK1
49 VDDLCPU
48 GNDLCPU
47 CPUCLK2
46 MREF66
45 VDD
44 SDRAM_F
43 SDRAM0
42 VDDSDR
41 GNDSDR
40 SDRAM1
39 SDRAM2
38 SDRAM3
37 GNDSDR
36 VDDSDR
35 SDRAM4
34 SDRAM5
33 VDDSDR
32 GNDSDR
31 SDRAM6
30 SDRAM7
29 FS1*
56-Pin 300mil SSOP
* These inputs have a 50K pull up to VDD.
Functionality
FS1
FS0
Power up Latched
REF1/CPU2_EN#
CPU0
CPU1,
MREF
1 1 1 66MHz
1 1 0 66MHz
1 0 X TCLK/2
01
X Reserved
0 0 X Tristate
CPU2
Tristate
66MHz
TCLK/2
Reserved
Tristate
Power Groups
VDD = REF, X1, X2
VDDPCI = PCICLK
VDDSDR = SDRAM
VDD48 = 3V48M
VDDLCPU = CPU
VDDLIOAPIC = IOAPIC, 2V48M
VDDA = PLL Core
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
1 page  
ICS9250-32
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Operating Supply
Current
Input Frequency
Input Capacitance
Transition time1
Settling time1
Clk Stabilization1
Skew1
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = Max loads;Select @ 66 MHz
IDD2.5OP
Fi
CIN
CINX
CL = Max loads;Select @ 66 MHz
VDD = 3.3 V
Logic Inputs
X1 & X2 oins
Ttrans To 1st crossing of target frequency
Ts From 1st crossing to 1% target frequency
TSTAB From VDD = 3.3 V to 1% target frequency
TCPU-IOAPIC CPU & IOAPIC @ 1.25 V
TCPU-PCI CPU @ 1.25 V, PCI @ 1.5 V
2
VSS-0.3
-5
-5
-200
27
1.5
1.5
VDD+0.3
0.8
5
251
27
14.312
2.3
2.1
280
100
5
45
3
3
3
3.5
3.5
V
V
µA
µA
mA
mA
MHz
pF
pF
ms
ms
ms
ns
ns
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
5
5 Page 
ICS9250-32
SY MBOL
A
A1
b
c
D
E
E1
e
h
L
N
α
In Millimeters
COMMON DIMENSIONS
MIN MA X
2.413
2.794
0.203
0.406
0.203
0.343
0.127
0.254
SEE V A RIA TIONS
10.033
10.668
7.391
7.595
0.635 BA SIC
0.381
0.635
0.508
1.016
SEE V A RIA TIONS
0° 8°
In Inc hes
COMMON DIMENSIONS
MIN MA X
.095
.110
.008
.016
.008
.0135
.005
.010
SEE V A RIA TIONS
.395
.420
.291
.299
0.025 BA SIC
.015
.025
.020
.040
SEE V A RIA TIONS
0° 8°
V A RIA TIONS
D mm.
N
MIN MA X
28
9.398
9.652
34
11.303
11.557
48
15.748
16.002
56
18.288
18.542
64
20.828
21.082
D (inc h)
MIN MA X
.370
.380
.445
.455
.620
.630
.720
.730
.820
J EDE C MO- 118
DOC# 10- 0034
.830
6 /1/0 0
R EVB
Ordering Information
ICS9250yF-32-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
11 this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ICS9250-32.PDF ] | |
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