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PDF IN74LV273 Data sheet ( Hoja de datos )

Número de pieza IN74LV273
Descripción Octal D-Type Flip-Flop
Fabricantes IK Semiconductor 
Logotipo IK Semiconductor Logotipo



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No Preview Available ! IN74LV273 Hoja de datos, Descripción, Manual

TECHNICAL DATA
Octal D Flip-Flop with Common Clock and Reset
IN74LV273
The IN74LV273 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT273.
The IN74LV273 has eight edge-triggered, D-type flip-flops with individual
D inputs and Q outputs. The common clock (CP) and master reset (MR)
inputs load and reset (clear) all flip-flops simultaneously. The state of each
D input, one set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Qn) of the flip-flop. All outputs
will be forced LOW independently of clock or data inputs by a LOW
voltage level on the MR input. The device is useful for applications where
the true output only is required and the clock and master reset are common
to all storage elements.
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
Supply voltage range: 1.2 to 5.5 V
Low input current: 1.0 µА; 0.1 µА at Т = 25 °С
High Noise Immunity Characteristic of CMOS Devices
N SUFFIX
PLASTIC DIP
20
1
20
1
DW SUFFIX
SO
ORDERING INFORMATION
IN74LV273N
Plastic DIP
IN74LV273DW
SOIC
TA = -40° to 125° C for all packages
LOGIC DIAGRAM
www.datasheet4u.cPPIoNIN1m020==GVNCCD
PIN ASSIGNMENT
RESET
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
1
2
3
4
5
6
7
8
9
10
20 V CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CLOCK
FUNCTION TABLE
Inputs
Reset Clock
D
LX
X
HH
HL
HL
X
HX
H= high level
L = low level
X = don’t care
Z = high impedance
Output
Q
L
H
L
no change
no change
1

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IN74LV273 pdf
IN74LV273
VOL and VOH are the typical output voltage drop that occur with the output load.
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
5

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