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PDF IN74LV74 Data sheet ( Hoja de datos )

Número de pieza IN74LV74
Descripción Dual D-Type Flip-Flop
Fabricantes IK Semiconductor 
Logotipo IK Semiconductor Logotipo



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No Preview Available ! IN74LV74 Hoja de datos, Descripción, Manual

TECHNICAL DATA
IN74LV74
Dual D-type flip-flop with set and reset;
positive-edge trigger
The IN74LV74 is a low-voltage Si-gate CMOS device and is pin
and function compatible with 74HC/HCT74.
The IN74LV74 is a dual positive edge triggered, D-type flip-flop
with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD)
inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable one set-up time prior to the LOW-to-
HIGH clock transition, for predictable operation. Schmitt-trigger action
in the clock input makes the circuit highly tolerant to slower clock rise
and fall times.
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
Supply voltage range: 1.2 to 3.6 V
Low input current: 1.0 µА; 0.1 µА at Т = 25 °С
High Noise Immunity Characteristic of CMOS Devices
N SUFFIX
PLASTIC
14
1
D SUFFIX
14
1
SOIC
ORDERING INFORMATION
IN74LV74N Plastic
IN74LV74D SOIC
TA = -40° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
RESET 1 1
DATA 1 2
CLOCK 1 3
SET 1 4
Q1 5
Q1 6
GND 7
14 V CC
13 RESET 2
12 DATA2
11 CLOCK 2
10 SET 2
9 Q2
8 Q2
www.datasheet4PuPINI.Nc102o0==mGVNCCD
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock Data Q
Q
LH X XHL
HL X XLH
L L X X H* H*
HH
HHL
HH
LLH
H H L X No Change
H H H X No Change
HH
X No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredictable
if Set and Reset go high simultaneously.
H= high level
L = low level
X = don’t care
Z = high impedance
1

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IN74LV74 pdf
IN74LV74
V M = 0.5 VCC
Figure 2. Switching Waveforms
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 3. Test Circuit
EXPANDED LOGIC DIAGRAM
(ONE FLIP-FLOP)
5

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