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PDF TC94A04AF Data sheet ( Hoja de datos )
| Número de pieza | TC94A04AF | |
| Descripción | 1 CHIP AUDIO DIGITAL PROCESSOR | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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TC94A04AF/AFD
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC94A04AF,TC94A04AFD
1 chip Audio Digital Processor
TC94A04AF/AFD is a single-chip audio Digital Signal Processor,
incorporating 4 way stereo analog switch, 2 ch AD converter, 4 ch
DA converter, and electronic volume for trimming.
It is possible to realize many applications, such as sound field
control -hall simulation, for example-, digital filter for equalizers,
surround, base boost and something.
TC94A04AF
Features
• Incorporates a 4 ch-stereo analog switch for AD converter
input.
• Incorporates a 1 ch stereo line-out.
TC94A04AFD
• Incorporates a 1 bit ∑ ∆-type AD converter (two channels).
THD: −82dB (typ.) S/N: 95dB (typ.)
• Incorporates a 1 bit ∑ ∆-type DA converter (four channels).
THD: −86dB (typ.) S/N: 98dB (typ.)
• Incorporates a trimming analog volume for each output of DA
converter. 0dB to −24dB (1dB step)
• As digital input/output port, this has 3 input port (6 ch) and 1
output port (2 ch), enabling input/output of sampling of 96
kHz/24 bit.
• Incorporates a built-in digital de-emphasis filter.
• Incorporates a digital attenuator.
• Incorporates a boot ROM to set a coefficient automatically,
Weight
QFP60-P-1414-0.80D: 1.08 g (typ.)
QFP80-P-1420-0.80B: 1.57 g (typ.)
which enables to transfer an initial data from built-in ROM/RAM to registers at the time of resetting
Boot ROM: 512 words
• The DSP block specifications are as follows:
Data bus: 24 bits
Multiplier/adder: 24 bits × 16 bits + 43 bits → 43 bits
Accumulator: 43 bits (sign extension: 4 bits)
Program ROM: 1024 words × 32 bits
Coefficient RAM: 384 words × 16 bits
Coefficient ROM: 256 words × 16 bits
Offset RAM: 16 words × 11 bits
Data RAM: 256 words × 24 bits
Interface buffer RAM: 32 words × 16 bits
Operation speed: 22.5 MIPS (510 step/fs: master clock = 768 fs, fs = 44.1 kHz)
Note 1: At the time of an analog input, approximately 170 steps (85 step/ch) in 510 step are used for the operation
of the decimation filter for AD converters.
• Incorporates data delay RAM (32 kbits).
Delay RAM: 2048 words × 16 bits (32 kbits)
• The microcontroller interface can be selected between Toshiba original 3 line mode and I2C mode.
• CMOS silicon structure supports high speed.
• Power supply is a single 5 V.
• The package are 60-pin and 80 pin flat package.
1 2001-11-15
1 page  
TC94A04AF/AFD
Pin No.
TC94A
04AF
TC94A
04AFD
(Note 3)
Symbol
I/O
32
45
DIN1
I Serial data input pin 1
Function
33
46
DIN0
I Serial data input pin 0
34
48
DOUT
O Serial data output pin
35 49 VDD Power pin
36
50
RST
I Reset pin
37 52 CS I Microcontroller interface chip select signal input pin
38
53
IFCK
I Microcontroller interface data shift clock input pin
39 54 IFDI I/O Microcontroller interface data input/output pin (I2C bus)
40
55
IFDO
O Microcontroller interface data output pin
41
57
ERR
O Error flag output pin
42
58
I2CS
I Microcontroller interface switching pin (I2C bus/Toshiba bus)
43
59
GND
GND pin
44
60
TST0
I Test pin 0
45
61
TST1
I Test pin 1
46
65
LIN4
I ADC-Lch signal input pin 4
47
66
LIN3
I ADC-Lch signal input pin 3
48
67
LIN2
I ADC-Lch signal input pin 2
49
68
LIN1
I ADC-Lch signal input pin 1
50
69
RIN4
I ADC-Rch signal input pin 4
51
70
RIN3
I ADC-Rch signal input pin 3
52
71
RIN2
I ADC-Rch signal input pin 2
53
72
RIN1
I ADC-Rch signal input pin 1
54 74 GNDAL Analog ground pin for ADC-Lch
55
75
OUTL
O Lch analog line-out pin
56
76
VRAL
I Reference voltage pin for ADC-Lch
57 78 VDALR Analog power pin for ADC-L/Rch
58
79
VRAR
I Reference voltage pin for ADC-Rch
59
80
OUTR
O Rch analgo lline-out pin
60 1 GNDAR Analog ground pin for ADC-Rch
Remarks
Schmitt input,
TTL/CMOS
(Note 2)
Schmitt input,
TTL/CMOS
(Note 2)
Schmidt input
Schmidt input
Schmidt input
Schmidt input
Open drain
output
Schmitt input
Note 2: 28 to 33 pin (TC94A04AF): Input level changes TTL/CMOS level by the command (42h: VS). Output is fixed
to CMOS level.
In case of TC94A04AFD, pin number are 39 to 41 pins and 43 to 46 pins.
Note 3: In case of TC94A04AFD, these are NC pins as below. Normally open, otherwise it connects to VDD or GND.
6, 10, 12, 16, 19, 22, 29, 31, 34, 36, 42, 44, 47, 51, 56, 62 to 64, 73, 77 pins.
5 2001-11-15
5 Page 
2.2 I2C Bus Mode
TC94A04AF/AFD
When I2CS = “H”, data can be transmitted or received in I2C bus mode.
When the CS signal is Low, control from the microcontroller is enabled.
In I2C mode, the CS signal can be used fixed to “L”. The IFCK signal is the transmit/receive clock.
The IFDI signal is the data.
The TC94A04AF/AFD loads the IFDI data on the IFCK signal rising edge.
When CS = “H”, IFCK and IFD signal are don't care.
2.2.1 Setting Registers
start 32h HZ
CS
IFCK
IFDI
(MCU →)
A7 A5 A3 A1
A6 A4 A2 A0
HZ HZ HZ
C7 C5 C3 C1
C6 C4 C2 C0
D15 D13 D11 D9
D14 D12 D10 D8
D7 D5 D3 D1
D6 D4 D2 65
end
An: I2C address
Cn: COMMAND
Dn: Data
The registers are set by command data using the IFDI signal.
The first byte after the I2C address (= 32h) is a command, which differs for each register. The data
sent after that are fixed to two bytes. Both command and data are sent starting from the MSB in I2C
format.
The data loaded internally every two bytes. Note that commands or data that must be switched on
the SYNC signal, such as the RUN command (command-44h) or the IFF flag (command-4Ah), must be
synchronized with the SYNC signal and loaded on that signal.
11 2001-11-15
11 Page | ||
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