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PDF IN74ACT109 Data sheet ( Hoja de datos )
| Número de pieza | IN74ACT109 | |
| Descripción | Dual J-K Positive-Edge-Triggered Flip-Flop | |
| Fabricantes | IK Semiconductor | |
| Logotipo |  |
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Dual J-K Flip-Flop
with Set and Reset
High-Speed Silicon-Gate CMOS
TECHNICAL DATA
IN74ACT109
The IN74ACT109 is identical in pinout to the LS/ALS109,
HC/HCT109. The IN74ACT109 may be used as a level converter for
interfacing TTL or NMOS outputs to High Speed CMOS inputs.
This device consists of two J-K flip-flops with individual set, reset,
and clock inputs. Changes at the inputs are reflected at the outputs with
the next low-to-high transition of the clock. Both Q to Q outputs are
available from each flip-flop.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25°C
• Outputs Source/Sink 24 mA
ORDERING INFORMATION
IN74ACT109N Plastic
IN74ACT109D SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheet4uP.PIcINNo81=6m=GVNCDC
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J K Q Q
LH
X XX H L
HL
LL
X XX L H
X
X X H*
H*
HH
LL L H
HH
H L Toggle
HH
L H No Change
HH
HH H L
HH
L X X No Change
X = Don’t care
*Both outputs will remain high as long as Set and
Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
1
1 page  
IN74ACT109
Figure 1. Switching Waveform
Figure 2. Switching Waveform
Figure 3. Switching Waveform
EXPANDED LOGIC DIAGRAM
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IN74ACT109.PDF ] | |
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