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PDF IN74LS161 Data sheet ( Hoja de datos )
| Número de pieza | IN74LS161 | |
| Descripción | 4-Bit Binary Counter | |
| Fabricantes | IK Semiconductor | |
| Logotipo |  |
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TECHNICAL DATA
Synchronous 4 Bit Counters; Binary,
Direct Reset
IN74LS161
This synchronous, presettable counter features an internal carry look-
ahead for application in high-speed counting designs. Synchronous
operation is provided by having all flip-flops clocked simultaneously so
that the outputs change conicident with each other when so instructed by
the count-enable inputs and internal gating.
This mode of operation eliminates the output counting spikes that are
normally associated with asynchronous (ripple clock) counters. A buffered
clock input triggers the four flip-flops on the rising (positive-going) edge
of the clock input wave form.
This counter is fully programmable; that is the outputs may be preset
to either level. As presetting is synchronous setting up a low level at the
load input disables the counter and causes the outputs to agree with the
setup data after the next clock pulse regardless of the levels of the enable
inputs.
The carry look-ahead circuitry provides for cascading counters for n-
bit synchronous applications without additional gating. Instrumental in
accomplishiing this function are two counter-enable inputs and a ripple
carry output. Both countenable inputs (ENABLE P and ENABLE T)
must be high to count, and ENABLE T is fed forward to enable the
ripple carry output. The ripple carry output thus enabled will produce a
high-level output pulse with a duration approximately equal to the high
level portion of the QA output. The high-level overflow ripple carry
pulse can be enable successive cascaded stages. Transitions at the
ENPor ENT are allowed regardless of the level of the clock input.
ORDERING INFORMATION
IN74LS161N Plastic
IN74LS161D SOIC
TA = 0° to 70° C for all packages
PIN ASSIGNMENT
• Internal Look-Ahead for Fast Counting
• Carry Output for n-Bit Cascading
• Synchronous Counting
• Synchronously Programmable
• Load Control Line
• Diode-Clamped Inputs
LOGIC DIAGRAM
www.datasheet4u.com
PIN 16 =VCC
PIN 8 = GND
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1 page  
IN74LS161
NOTES A. CL includes probe and jig capacitance.
B. All diodes are 1N916 or 1N3064.
Figure 5. Test Circuit
Sequence illustrated in waveforms:
1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one, and two.
4. Inhibit.
Figure 7. Timing Diagram
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| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IN74LS161.PDF ] | |
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