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PDF IN74HCT109A Data sheet ( Hoja de datos )
| Número de pieza | IN74HCT109A | |
| Descripción | Dual J-K Positive-Edge-Triggered Flip-Flop | |
| Fabricantes | IK Semiconductor | |
| Logotipo |  |
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TECHNICAL DATA
Dual J-K Flip-Flop
with set and Reset
High-Performance Silicon-Gate CMOS
IN74HCT109A
The IN74HCT109A is identical in pinout to the LS/ALS109. The
IN74HCT109A may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
This device consists of two J-K flip-flops with individual set, reset, and
clock inputs. Changes at the inputs are reflected at the outputs with the next
low-to-high transition of the clock. Both Q to Q outputs are available from
each flip-flop.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
IN74HCT109AN Plastic
IN74HCT109AD SOIC
TA = -55° to 125° C for all packages.
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheet4PuPIINN.c81=6o=GVmNCDC
FUNCTION TABLE
Inputs
Output
Set Reset Clock J K Q Q
LH
X XX H L
HL
LL
X XX L H
X X X H* H*
HH
LL L H
HH
H L Toggle
HH
L H No Change
HH
HH H L
HH
L X X No Change
X = Don’t care
*Both outputs will remain high as long as Set and
Reset are low., but the output states are
unpredictable if Set and Reset go high
simultaneously.
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1 page  
IN74HCT109A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
EXPANDED LOGIC DIAGRAM
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5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IN74HCT109A.PDF ] | |
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| Número de pieza | Descripción | Fabricantes |
| IN74HCT109A | Dual J-K Positive-Edge-Triggered Flip-Flop | IK Semiconductor |
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