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PDF IN74AC533 Data sheet ( Hoja de datos )

Número de pieza IN74AC533
Descripción Octal D-Type Latch
Fabricantes IK Semiconductor 
Logotipo IK Semiconductor Logotipo



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No Preview Available ! IN74AC533 Hoja de datos, Descripción, Manual

TECHNICAL DATA
Octal 3-State Inverting
Transparent Latch
High-Speed Silicon-Gate CMOS
IN74AC533
The IN74AC533 is identical in pinout to the LS/ALS533,
HC/HCT533. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. The data appears as the
outputs in inverted form. When Latch Enable goes low, data meeting the
setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the high-
impedance state. Thus, data may be latched even when the outputs are not
enabled.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA; 0.1 µA @ 25°C
High Noise Immunity Characteristic of CMOS Devices
Outputs Source/Sink 24 mA
3-State Outputs for Bus Interfacing
ORDERING INFORMATION
IN74AC533N Plastic
IN74AC533DW SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheet4u.cPPIoNINm1020==GVNCCD
FUNCTION TABLE
Inputs
Output Latch
Enable Enable
LH
LH
LL
D
H
L
X
H XX
X = don’t care
Z = high impedance
Output
Q
L
H
no
change
Z
1

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IN74AC533 pdf
IN74AC533
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
EXPANDED LOGIC DIAGRAM
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