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PDF IN74HC112A Data sheet ( Hoja de datos )
| Número de pieza | IN74HC112A | |
| Descripción | Dual J-K Negative-Edge-Triggered Flip-Flop | |
| Fabricantes | IK Semiconductor | |
| Logotipo |  |
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TECHNICAL DATA
Dual J-K Flip-Flop
with Set and Reset
High-Performance Silicon-Gate CMOS
IN74HC112A
The IN74HC112A is identical in pinout to the LS/ALS112. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
Each flip-flop is negative-edge clocked and has active-low
asynchronous Set and Reset inputs.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC112AN Plastic
IN74HC112AD SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
www.datasheetPP4IINNu81.=6c=GVoNCDCm
FUNCTION TABLE
Inputs
Outputs
Set Reset Clock J K Q
Q
LH
X XX H L
HL
LL
X XX L H
X X X L* L*
HH
L L No Change
HH
LH L
H
HH
HL H
L
HH
HH
Toggle
HH
L X X No Change
HH
H X X No Change
HH
X X No Change
* Both output will remain low as long as Set and Reset are
low, but the output states are unpredictable if Set and Reset
go high simultaneously
X = Don’t Care
1
1 page  
IN74HC112A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IN74HC112A.PDF ] | |
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| Número de pieza | Descripción | Fabricantes |
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