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PDF XC2C512 Data sheet ( Hoja de datos )
| Número de pieza | XC2C512 | |
| Descripción | Coolrunner-ii CPLD | |
| Fabricantes | Xilinx | |
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R XC2C512 CoolRunner-II CPLD
DS096 (v3.2) March 8, 2007
00
Features
• Optimized for 1.8V systems
- As fast as 7.1 ns pin-to-pin delays
- As low as 14 μA quiescent current
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
• Available in multiple package options
- 208-pin PQFP with 173 user I/O
- 256-ball FT (1.0mm) BGA with 212 user I/O
- 324-ball FG (1.0mm) BGA with 270 user I/O
- Pb-free available for all packages
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Unsurpassed low power management
· DataGATE enable signal control
- Four separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (divide by 2,4,6,8,10,12,14,16)
· CoolCLOCK
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
macrocell
· Multiple global output enables
· Global set/reset
- Advanced design security
- PLA architecture
· Superior pinout retention
· 100% product term routability across function
block
- Open-drain output option for Wired-OR and LED
drive
- Optional bus-hold, 3-state or weak pullup on
selected I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
· SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
- Hot Pluggable
Refer to the CoolRunner™-II family data sheet for architec-
ture description.
Product Specification
Description
The CoolRunner-II 512-macrocell device is designed for
both high performance and low power applications. This
lends power savings to high-end communication equipment
and high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved
This device consists of thirty two Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt-trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as "direct input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as
a synchronous clock source. Macrocell registers can be
individually configured to power up to the zero or one state.
A global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
Circuitry has also been included to divide one externally
supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.
The use of the clock divide (division by 2) and DualEDGE
flip-flop gives the resultant CoolCLOCK feature.
DataGATE is a method to selectively disable inputs of the
CPLD that are not of interest during certain points in time.
© 2002-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS096 (v3.2) March 8, 2007
Product Specification
www.xilinx.com
1
1 page  
R XC2C512 CoolRunner-II CPLD
Symbol
VOH
Parameter
High level output voltage
VOL Low level output voltage
Notes:
1. Hysteresis used on 1.5V inputs.
Test Conditions
IOH = –8 mA, VCCIO = 1.4V
IOH = –0.1 mA, VCCIO = 1.4V
IOL = 8 mA, VCCIO = 1.4V
IOL = 0.1 mA, VCCIO = 1.4V
Min.
VCCIO – 0.45
VCCIO – 0.2
-
-
Max.
-
-
0.4
0.2
Units
V
V
V
V
Schmitt Trigger Input DC Voltage Specifications
Symbol
Parameter
Test Conditions
VCCIO
VT+
VT-
Input source voltage
Input hysteresis threshold voltage
Min.
1.4
0.5 x VCCIO
0.2 x VCCIO
Max.
3.9
0.8 x VCCIO
0.5 x VCCIO
Units
V
V
V
SSTL2-1 DC Voltage Specifications
Symbol
Parameter
Test Conditions
Min. Typ Max.
VCCIO Input source voltage
2.3 2.5
2.7
VREF(1) Input reference voltage
1.15
1.25
1.35
VTT(2) Termination voltage
VREF – 0.04 1.25
VREF + 0.04
VIH High level input voltage
VREF + 0.18
-
3.9
VIL Low level input voltage
–0.3
- VREF – 0.18
VOH High level output voltage IOH = –8 mA, VCCIO = 2.3V VCCIO – 0.62 -
-
VOL Low level output voltage IOL = 8 mA, VCCIO = 2.3V - - 0.54
Notes:
1. VREF should track the variations in VCCIO, also peak to peak AC noise on VREF may not exceed ±2% VREF
2. VTT of transmitting device must track VREF of receiving devices
Units
V
V
V
V
V
V
V
SSTL3-1 DC Voltage Specifications
Symbol
Parameter
Test Conditions
Min.
Typ Max.
VCCIO Input source voltage
3.0 3.3 3.6
VREF(1) Input reference voltage
1.3 1.5 1.7
VTT(2)
Termination voltage
VREF – 0.05 1.5 VREF + 0.05
VIH High level input voltage
VREF + 0.2
- VCCIO + 0.3
VIL Low level input voltage
–0.3
- VREF – 0.2
VOH
High level output voltage IOH = –8 mA, VCCIO = 3V
VCCIO – 1.1
-
-
VOL Low level output voltage IOL = 8 mA, VCCIO = 3V - - 0.7
Notes:
1. VREF should track the variations in VCCIO, also peak to peak AC noise on VREF may not exceed ±2% VREF
2. VTT of transmitting device must track VREF of receiving devices
Units
V
V
V
V
V
V
V
DS096 (v3.2) March 8, 2007
Product Specification
www.xilinx.com
5
5 Page 
R
Pin11 Descriptions
Function Macro-
Block
cell PQ208
1(GTS0)
1
7
1 26
1(GTS3)
3
5
1 44
1 5-
1 6-
1 7-
1 8-
1 9-
1 10 -
1 11 -
1 12 -
1(GTS2)
13
3
1 14 2
1 15 208
1(GSR) 16 206
2 1-
2 28
2 3-
2 4-
2 5-
2 6-
2 7-
2 8-
2 9-
2 10 -
2 11 -
2 12 -
2 13 -
2(GTS1)
14
9
2 15 10
2 16 12
FT256
D4
B2
E3
C3
-
-
-
-
-
-
-
-
D3
B3
B4
C4
A1
-
D2
-
-
-
-
-
-
-
-
-
C2
E5
B1
E4
FG324
C1
C2
B1
B2
-
-
-
-
-
-
-
-
D3
C3
A1
A2
D2
D1
F4
F3
-
-
-
-
-
-
-
-
E2
E1
F2
G4
I/O
Bank
2
2
2
2
-
-
-
-
-
-
-
-
2
2
2
2
2
2
2
2
-
-
-
-
-
-
-
-
2
2
2
2
XC2C512 CoolRunner-II CPLD
Pin Descriptions (Continued)
Function Macro-
Block
cell PQ208 FT256 FG324
3 1 205 - B3
3 2 - A2 C4
3 3 203 - B4
3 4 - C5 C5
3
5
202 A3
B5
3 6 ---
3 7 ---
3 8 ---
3 9 ---
3 10 - - -
3 11 - - -
3 12 - - -
3 13 201 E7 A3
3 14 - A4 A4
3 15 200 C6 D6
3 16 199 B5 A5
4 1 - C1 G3
4 2 14 E2 G2
4 3 - F2 G1
4 4 15 E6 H4
4 5 ---
4 6 ---
4 7 ---
4 8 ---
4 9 ---
4 10 - - -
4 11 - - -
4 12 - - -
4 13 - F3 H3
4 14 16 D1 H2
4 15 17 G4 H1
4 16 18 E1 J4
I/O
Bank
2
2
2
2
2
-
-
-
-
-
-
-
2
2
2
2
2
2
2
2
-
-
-
-
-
-
-
-
2
2
2
2
DS096 (v3.2) March 8, 2007
Product Specification
www.xilinx.com
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet XC2C512.PDF ] | |
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