DataSheet.es    


PDF XC2C128 Data sheet ( Hoja de datos )

Número de pieza XC2C128
Descripción (XC2C32 - XC2C512) Coolrunner-ii CPLD Family
Fabricantes Xilinx 
Logotipo Xilinx Logotipo



Hay una vista previa y un enlace de descarga de XC2C128 (archivo pdf) en la parte inferior de esta página.


Total 16 Páginas

No Preview Available ! XC2C128 Hoja de datos, Descripción, Manual

0
R CoolRunner-II CPLD Family
DS090 (v3.1) September 11, 2008
0 0 Product Specification
Features
• Optimized for 1.8V systems
- Industry’s fastest low power CPLD
- Densities from 32 to 512 macrocells
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- On-The-Fly Reconfiguration (OTF)
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt trigger input (per pin)
- Multiple I/O banks on all devices
- Unsurpassed low power management
· DataGATE external signal control
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (÷ 2,4,6,8,10,12,14,16)
· CoolCLOCK
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
macrocell
· Multiple global output enables
· Global set/reset
- Abundant product term clocks, output enables and
set/resets
- Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
- Advanced design security
- Open-drain output option for Wired-OR and LED
drive
- Optional bus-hold, 3-state or weak pullup on select
I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels on all parts
- SSTL2_1,SSTL3_1, and HSTL_1 on 128
macrocell and denser devices
- Hot pluggable
• PLA architecture
- Superior pinout retention
- 100% product term routability across function block
• Wide package availability including fine pitch:
- Chip Scale Package (CSP) BGA, Fine Line BGA,
TQFP, PQFP, VQFP, and QFN packages
- Pb-free available for all packages
• Design entry/verification using Xilinx and industry
standard CAE tools
• Free software support for all densities using Xilinx®
WebPACK™ tool
• Industry leading nonvolatile 0.18 micron CMOS
process
- Guaranteed 1,000 program/erase cycles
- Guaranteed 20 year data retention
Family Overview
Xilinx CoolRunner™-II CPLDs deliver the high speed and
ease of use associated with the XC9500/XL/XV CPLD fam-
ily with the extremely low power versatility of the XPLA3
family in a single CPLD. This means that the exact same
parts can be used for high-speed data communications/
computing systems and leading edge portable products,
with the added benefit of In System Programming. Low
power consumption and high-speed operation are com-
bined into a single family that is easy to use and cost effec-
tive. Clocking techniques and other power saving features
extend the users’ power budget. The design features are
supported starting with Xilinx ISE® 4.1i WebPACK tool.
Additional details can be found in Further Reading,
page 14.
Table 1 shows the macrocell capacity and key timing
parameters for the CoolRunner-II CPLD family.
Table 1: CoolRunner-II CPLD Family Parameters
XC2C32A XC2C64A
XC2C128
XC2C256
XC2C384
XC2C512
Macrocells
32 64 128 256 384 512
Max I/O
33 64 100 184 240 270
TPD (ns)
3.8 4.6
5.7
5.7
7.1 7.1
TSU (ns)
1.9 2.0
2.4
2.4
2.9 2.6
TCO (ns)
3.7 3.9
4.2
4.5
5.8 5.8
FSYSTEM1 (MHz)
323
263
244
256
217 179
© 2002–2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS090 (v3.1) September 11, 2008
Product Specification
www.xilinx.com
1

1 page




XC2C128 pdf
R CoolRunner-II CPLD Family
Macrocell
The CoolRunner-II CPLD macrocell is extremely efficient
and streamlined for logic creation. Users can develop sum
of product (SOP) logic expressions that comprise up to 40
inputs and span 56 product terms within a single function
block. The macrocell can further combine the SOP expres-
sion into an XOR gate with another single p-term expres-
sion. The resulting logic expression’s polarity is also
selectable. As well, the logic function can be pure combina-
torial or registered, with the storage element operating
selectably as a D or T flip-flop, or transparent latch. Avail-
able at each macrocell are independent selections of global,
function block level or local p-term derived clocks, sets,
resets, and output enables. Each macrocell flip-flop is con-
figurable for either single edge or DualEDGE clocking, pro-
viding either double data rate capability or the ability to
distribute a slower clock (thereby saving power). For single
edge clocking or latching, either clock polarity can be
selected per macrocell. CoolRunner-II CPLD macrocell
details are shown in Figure 3. Note that in Figure 4, stan-
dard logic symbols are used except the trapezoidal multi-
plexers have input selection from statically programmed
configuration select lines (not shown). Xilinx application
note XAPP376 gives a detailed explanation of how logic is
created in the CoolRunner-II CPLD family.
From AIM
40
49 P-terms
4 P-terms
To PTA, PTB, PTC of
other macrocells
CTC, CTR,
CTS, CTE
Direct Input
from
I/O Block
PTA
PTB
PTC
VCC
PTA
CTS
GSR
GND
GND
PLA OR Term
CTC
PTC
GCK0
GCK1
GCK2
PTA
CTR
GSR
GND
Feedback
to AIM
S
D/T
Q
PTC CE FIF
Latch
CK DualEDGE
R
To I/O Block
Figure 3: CoolRunner-II CPLD Macrocell
DS090_03_121201
When configured as a D-type flip-flop, each macrocell has
an optional clock enable signal permitting state hold while a
clock runs freely. Note that Control Terms (CT) are available
to be shared for key functions within the FB, and are gener-
ally used whenever the exact same logic function would be
repeatedly created at multiple macrocells. The CT product
terms are available for FB clocking (CTC), FB asynchro-
nous set (CTS), FB asynchronous reset (CTR), and FB out-
put enable (CTE).
Any macrocell flip-flop can be configured as an input regis-
ter or latch, which takes in the signal from the macrocell’s
I/O pin, and directly drives the AIM. The macrocell combina-
tional functionality is retained for use as a buried logic node
if needed. FToggle is the maximum clock frequency to which
a T flip-flop can reliably toggle.
Advanced Interconnect Matrix (AIM)
The Advanced Interconnect Matrix is a highly connected
low power rapid switch. The AIM is directed by the software
to deliver up to a set of 40 signals to each FB for the cre-
ation of logic. Results from all FB macrocells, as well as, all
pin inputs circulate back through the AIM for additional con-
nection available to all other FBs as dictated by the design
DS090 (v3.1) September 11, 2008
Product Specification
www.xilinx.com
5

5 Page





XC2C128 arduino
R CoolRunner-II CPLD Family
Timing Model
Figure 11 shows the CoolRunner-II CPLD timing model. It
represents one aspect of the overall architecture from a tim-
ing viewpoint. Each little block is a time delay that a signal
incurs if the signal passes through such a resource. Timing
reports are created by tallying the incremental signal delays
as signals progress within the CPLD. Software creates the
timing reports after a design has been mapped onto the
specific part, and knows the specific delay values for a given
speed grade. Equations for the higher level timing values
(i.e., TPD and FSYSTEM) are available. Table 6 summarizes
the individual parameters and provides a brief definition of
their associated functions. Xilinx application note XAPP375
details the CoolRunner-II CPLD family timing with several
examples.
TLOGI2
TF
TPDI
TIN
TDIN
TGCK
TGSR
THYS
THYS
THYS
TLOGI1
TCT
D/T TCOI
TSUI THI
TECSU
TECHO
CE TAOI
S/R
TOUT
TOEM
TGTS
THYS
THYS
Figure 11: CoolRunner-II CPLD Timing Model
Note: Always refer to the timing report in ISE Software for accurate timing values for paths.
TEN
TSLEW
XAPP375_03_010303
Table 6: Timing Parameter Definitions
Symbol
Parameter
Buffer Delays
TlN Input Buffer Delay
TDIN
Direct data register input delay
TGCK
Global clock (GCK) buffer delay
TGSR
Global set/reset (GSR) buffer delay
TGTS
Global output enable (GTS) buffer delay
TOUT
Output buffer delay
TEN Output buffer enable/disable delay
TSLEW
Output buffer slew rate control delay
P-term Delays
TCT
TLOGI1
TLOGI2
Control Term delay (single PT or FB-CT)
Single P-term logic delay
Multiple P-term logic delay adder
Table 6: Timing Parameter Definitions (Continued)
Symbol
Parameter
Macrocell Delays
TPDI
Macrocell input to output valid
TSUI
Macro register setup before clock
THI Macro register hold after clock
TECSU
Macro register enable clock setup time
TECHO
Macro register enable clock hold time
TCOI
Macro register clock to output valid
TAOI Macro register set/reset to output valid
THYS
Hysteresis selection delay adder
Feedback Delays
TF
TOEM
Feedback delay
Macrocell to Global OE delay
DS090 (v3.1) September 11, 2008
Product Specification
www.xilinx.com
11

11 Page







PáginasTotal 16 Páginas
PDF Descargar[ Datasheet XC2C128.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
XC2C128(XC2C32 - XC2C512) Coolrunner-ii CPLD FamilyXilinx
Xilinx

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar