DataSheet.es    


PDF ICS1526 Data sheet ( Hoja de datos )

Número de pieza ICS1526
Descripción Video Clock Synthesizer
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



Hay una vista previa y un enlace de descarga de ICS1526 (archivo pdf) en la parte inferior de esta página.


Total 11 Páginas

No Preview Available ! ICS1526 Hoja de datos, Descripción, Manual

Integrated Circuit Systems
Preliminary Data Sheet
ICS1526
Video Clock Synthesizer
General Description
The ICS1526 is a low-cost, high-performance
frequency generator. It is suited to general purpose
phase controlled clock synthesis as well as
line-locked and genlocked high-resolution video
applications. Using ICS’s advanced low-voltage
CMOS mixed-mode technology, the ICS1526 is an
effective clock synthesizer that supports video
projectors and displays at resolutions from VGA to
beyond XGA.
The ICS1526 offers single-ended clock outputs to 200
MHz. The HSYNC_out, and VSYNC_out pins provide
the regenerated versions of the HSYNC and VSYNC
inputs synchronous to the CLK output.
The advanced PLL uses its internal programmable
feedback divider. The device is programmed by a
standard I2C-bus™ serial interface and is available in
a TSSOP16 package.
ICS1526 Functional Diagram
OSC
HSYNC
VSYNC
I2C
ICS1526
HSYNC_out
VSYNC_out
CLK
LOCK
Features
• Lead-free packaging (Pb-free)
• Low jitter (typical 27 ps short term jitter)
• Wide input frequency range
• 8 kHz to 100 MHz
• LVCMOS single-ended clock outputs
• Up to 200 MHz
• Uses 3.3 V power supply
• 5 Volt tolerant Inputs (HSYNC, VSYNC)
• Coast (ignore HSYNC) capability via VSYNC pin
• Industry standard I2C-bus programming interface
• PLL Lock detection via I2C or LOCK output pin
• 16-pin TSSOP package
Applications
• Frequency synthesis
• LCD monitors, video projectors and plasma displays
• Genlocking multiple video subsystems
Pin Configuration (16-pin TSSOP)
VSSD
SDA
SCL
VSYNC
HSYNC
VDDA
VSSA
OSC
1
2
3
4
5
6
7
8
16 VDDD
15 VSSQ
14 VSYNC_out
13 VDDQ
12 CLK
11 HSYNC_out
10 LOCK
9 I2CADR
MDS 1526 I
ICS reserves the right to make changes in the preliminary device data
identified in this publication without notice. ICS advises its customers
to obtain the latest version of all device data to verify that information
being relied upon is current and accurate.
Revision 020304

1 page




ICS1526 pdf
ICS1526 Preliminary Data Sheet
Section 3 Register map summary
Section 3 Register map summary
Word
Address
00h
Name
Input
Control
Access Bit Name
Reset
Bit# Value
Description
R/W
CPen
0 1 Charge Pump Enable
0=External Enable via VSYNC, 1=Always Enabled
VSYNC_Pol 1
0 VSYNC Polarity (Charge Pump Enable)
Requires 00h:0=0
0=Coast (charge pump disabled) while VSYNC low,
1=Coast (charge pump disabled) while VSYNC high
HSYNC_Pol 2
0 HSYNC Polarity
0=Rising Edge, 1=Falling Edge
Reserved
3
0 Reserved
Reserved
4
0 Part requires a 0 for correct operation
Reserved
5
0 Reserved
EnPLS
6 1 Enable PLL Lock Output
0=Disable, 1=Enable
Reserved
7
0 Reserved
01h
Loop
R/W
ICP0-2
0-2
Control*
Reserved
VCOD0-1
3
4-5
Reserved
6-7
ICP (Charge Pump Current)
Bit 2,1,0 = {000 =1 µA, 001 = 2 µA, 010 = 4 µA... 110 = 64 µA, 111 =
128 µA}
Reserved
VCO Divider
Bit 5,4 = {00 = ÷2, 01=÷4, 10=÷8, 11=÷16}
Reserved
02h
FdBk Div R / W
FBD0-7
0-7
0*
Feedback Divider LSBs (bits 0-7)
03h
FdBk Div R / W
FBD8-11
0-3
1*
Reserved
4-7
Feedback Divider MSBs (bits 8-11)
Divider setting = 12-bit word + 8
Minimum 12 = 000000000100
Maximum 4103 =111111111111
Reserved
04h Reserved
Reserved
0-7
0 Reserved
05h
Schmitt- R / W
Schmitt
0 1 Schmitt-trigger control
trigger*
control
0=Schmitt-trigger, 1=No Schmitt-trigger
Metal_Rev 1-7
0 Metal Mask Revision Number
06h
Output R / W
Reserved
0
0 Reserved
Enables
OE 1 0 Output Enable for CLK, HSYNC_out, VSYNC_out
0=High Impedance (disabled), 1=Enabled
Reserved
2-7
0 Reserved
MDS1526 I
5
Revision 020304
Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel (408) 297-1201 www.icst.com

5 Page





ICS1526 arduino
ICS1526 Preliminary Data Sheet
Section 6 Package Outline and Package Dimensions
Section 6 Package Outline and Package Dimensions
16-pin TSSOP 4.40 mm body, 0.65 mm pitch
Package dimensions are kept current with JEDEC Publication No. 95
16
Millimeters
Inches
INDEX
AREA
12
D
A2
e
b
E1 E
A
A1
-C-
SEATING
PLANE
aaa C
Symbol
A
A1
A2
b
C
D
E
E1
e
L
α
aaa
Min Max
-- 1.20
0.05 0.15
0.80 1.05
0.19 0.30
0.09 0.20
4.90
5.1
6.40 BASIC
4.30 4.50
0.65 Basic
0.45 0.75
0° 8°
-- 0.10
Min Max
-- 0.047
0.002 0.006
0.032 0.041
0.007 0.012
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
0.018 0.030
0° 8°
-- 0.004
c
L
Section 7 Ordering Information
Part / Order Number
ICS1526GLF
ICS1526GLFTR
Marking
1526GLF
1526GLF
Shipping Packaging
Tubes
Tape & Reel
Package
16-pin TSSOP
16-pin TSSOP
Temperature
0 to +70° C
0 to +70° C
“LF” denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS1526 I
11
Revision 020304
Integrated Circuit Systems, 525 Race Street, San Jose, CA 95126, tel (408) 297-1201 www.icst.com

11 Page







PáginasTotal 11 Páginas
PDF Descargar[ Datasheet ICS1526.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
ICS1522User-Programmable Video Clock Generator/ Line-Locked Clock RegeneratorIntegrated Circuit Systems
Integrated Circuit Systems
ICS1523High-Performance Programmable Line-Locked Clock GeneratorIntegrated Circuit Systems
Integrated Circuit Systems
ICS1524Dual Output Phase Controlled SSTL-3/PECL Clock GeneratorIntegrated Circuit Systems
Integrated Circuit Systems
ICS1526Video Clock SynthesizerIntegrated Circuit Systems
Integrated Circuit Systems

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar