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PDF ICS1574B Data sheet ( Hoja de datos )
| Número de pieza | ICS1574B | |
| Descripción | User Programmable Laser Engine Pixel Clock Generator | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS1574B
User Programmable Laser Engine Pixel Clock Generator
Description
The ICS1574B is a very high performance monolithic phase-
locked loop (PLL) frequency synthesizer designed for laser
engine applications. Utilizing ICS’s advanced CMOS mixed-
mode technology, the ICS1574B provides a low cost solution
for high-end pixel clock generation for a variety of laser en-
gine product applications.
The pixel clock output (PCLK) frequency is derived from the
main clock by a programmable resettable divider.
Operating frequencies are fully programmable with direct
control provided for reference divider, feedback divider and
post-scaler.
Block Diagram
Features
• Supports high resolution laser graphics. PLL/VCO
frequency re-programmable through serial interface
port to 400 MHz; allows less than ±1.5ns pixel clock
resolution.
• Laser pixel clock output is synchronized with
conditioned beam detect input
• Ideal for laser printer, copier and FAX pixel clock
applications
• On-chip PLL with internal loop filter
• On-chip XTAL oscillator frequency reference
• Resettable, programmable counter gives glitch-free
clock alignment
• Single 5 volt power supply
• Low power CMOS technology
• Compact – 16-pin 0.150" skinny SOIC package
• User re-programmable clock frequency supports
zoom and gray scale functions
1574B 8/31/00
Figure 1
1 page  
ICS1574B
Reference Oscillator
and Crystal Selection
The ICS1574B has circuitry on-board to implement a
Pierce oscillator with the addition of only one external
component, a quartz crystal. Pierce oscillators operate the
crystal
in
anti- (also called parallel-) resonant mode. See the AC
Characteristics for the effective capacitive loading to
specify when ordering crystals.
Series-resonant crystals may also be used with the
ICS1574B. Be aware that the oscillation frequency will be
slightly higher than the frequency that is stamped on the
can (typically 0.025 – 0.05%).
As the entire operation of the phase-locked loop depends
on having a stable reference frequency, we recommend
that the crystal be mounted as closely as possible to the
package. Avoid routing digital signals or the ICS1574B
outputs underneath or near these traces. It is also desirable
to ground the crystal can to the ground plane, if possible.
If an external reference frequency source is to be used with
the ICS1574B, it is important that it be jitter-free. The ris-
ing and falling edges of that signal should be fast and free
of noise for best results.
The loop phase can be locked to either the rising or falling
edges of the XTAL1 input signals, and is controlled by
Bit 56.
Power-On Initialization
The ICS1574B has an internal power-on reset circuit that
performs the following functions:
1) Selects the modulus of the PCLK divider to
be four (4).
2) Sets the multiplexer to pass the reference
frequency to PCLK divider input.
These functions should allow initialization for most appli-
cations that cannot immediately provide for register
programming upon system power-up.
Because the power-on reset circuit is on the VDD supply,
and because that supply is filtered, care must be taken to
allow the reset to de-assert before programming. A safe
guideline is to allow 20 microseconds after the VDD sup-
ply reaches 4 volts.
Programming Notes
• VCO Frequency Range: Use the post-divider to keep the
VCO frequency as high as possible within its operating
range.
• Divider Range: For best results in normal situations
keep the reference divider modulus as short as possible
(for a frequency at the output of the reference divider in
the few hundred kHz to several MHz range). If you
need to go to a lower phase comparator reference fre-
quency (usually required for increased frequency
accuracy), that is acceptable, but jitter performance will
suffer somewhat.
• VCO Gain Programming: Use the minimum gain which
can reliably achieve the VCO frequency desired, as
shown here:
VCO GAIN
4
5
6
7
MAX FREQUENCY
100 MHz
200 MHz
300 MHz
400 MHz
• Phase Detector Gain: For most applications and divider
ranges, set P [1, 0] = 10 and set P[2] = 1. Under some
circumstances, setting the P [2] bit “on” can reduce
jitter. During operation at exact multiples of the crystal
frequency, P[2] bit = 0 may provide the best jitter per-
formance.
Board Test Support
It is often desirable to statically control the levels of the
output pins for circuit board test. The ICS1574B supports
this through a register programmable mode, AUX-EN.
When this mode is set, a register bit directly controls the
logic level of the PCLK pin. This mode is activated when
the S[0] and S[1] bits are both set to logic 1. See Register
Mapping for details.
5
5 Page 
ICS1574B
Absolute Maximum Ratings
VDD, VDDO (measured to VSS) . . . . . . . . 7.0V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.5V to VDD +0.5V
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . VSS – 0.5V to VDDO +0.5V
Ambient Operating Temperature . . . . . . . – 55° C to +125° C
Storage Temperature . . . . . . . . . . . . . . . . . – 65° C to +150° C
Junction Temperature . . . . . . . . . . . . . . . . . 175° C
Soldering Temperature . . . . . . . . . . . . . . . . 260° C
Recommended Operating Conditions
VDD, VDDO (measured to VSS) . . . . . . . . 4.75 to 5.25 V
Operating Temperature (Ambient) . . . . . . 0 to +70°C
DC Electrical Characteristics
TTL-Compatible Inputs (DATCLK, DATA, HOLD, PCLKEN)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Capacitance
Hysterisis (DATCLK input)
SYMBOL
VIH
VIL
IIH
IIL
CIN
VHYS
CONDITIONS
VIH = VDD
VIL = 0.0
VDD = 5V
MIN
2.0
VSS –0.5
—
—
—
.20
MAX
VDD +0.5
0.8
10
200
8
.60
UNITS
V
V
µA
µA
pF
V
XTAL1 Input (External Reference Frequency)
PARAMETER
SYMBOL
Input High Voltage
VXH
Input Low Voltage
VXL
CONDITIONS
MIN
3.75
VSS –0.5
MAX
VDD +0.5
1.25
UNITS
V
V
PCLK
PARAMETER
Output High Voltage (IOH = 4.0mA)
Output Low Voltage (IOL = 8.0mA)
SYMBOL CONDITIONS
MIN
2.4
—
MAX
—
0.4
UNITS
V
V
11
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ICS1574B.PDF ] | |
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