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PDF ICS1886 Data sheet ( Hoja de datos )

Número de pieza ICS1886
Descripción FDDI / Fast Ethernet PHYceiverTM
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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No Preview Available ! ICS1886 Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
ICS1886
FDDI / Fast Ethernet PHYceiverTM
General Description
The ICS1886 is designed to provide high performance clock
recovery and generation for either 32.064 Mb/s, 34.368
Mb/s, 125 Mb/s or 139.264 Mb/s NRZ or NRZI serial data
streams. The ICS1886 is ideally suited for LAN transceiver
applications in either European or Japanese communication
environments.
The ICS1886 also operates at the 100Mbit Ethernet
frequency of 125 MHz. This is ideal for serial Ethernet data
applications where no serial to parallel conversion is
required.
Clock and data recovery is performed on an input serial data
stream or the buffered transmit data depending upon the state
of the loopback input. A continuous clock source will
continue to be present even in the absence of input data. All
internal timing is derived from either a low cost crystal or an
external clock module.
Features
• Data and clock recovery for: 32.064 Mb/s (Japan)
34.368 Mb/s (Europe - E3) 125 MHz (Ethernet)
139.264 Mb/s (Europe - E4)
• Clock multiplication from either a crystal, differential
or single-ended timing source
• Continuous clock in the absence of data
• No external PLL components
• Lock/Loss status indicator output
• Loopback mode for system diagnostics
• Selectable loop timing mode
• PECL drivers with settable sink current
The ICS1886 utilizes advanced CMOS phase-locked loop
technology which combines high performance and low
Pin Configuration
power at a greatly reduced cost.
Block Diagram
ICS1886RevC120996
28-Pin SOIC
PHYceiver is a trademark of Integrated Circuit Systems, Inc.

1 page




ICS1886 pdf
ICS1886
AC Characteristics
VDD = VMIN to VMAX, VSS = 0V, TA = TMIN to TMAX
PARAMETER
Rise/Fall Time
Recovered clock
Duty Cycle
Output Data Setup
Output Data Hold
Transmit Latency
Recieve Latency
Lock Acquisition
Capture Range
Receive Jitter Tolerance
Transmit Clock Stability
SYMBOL CONDITIONS
ECL Outputs
tr, tf 15pF Load
MIN
1.4
tDC 15pF Load
45
tsv W.R.T. RC at 139.264MHz
2.2
thd W.R.T. RC at 139.264MHz
3.9
TL 139.264MHz
6
RL 139.264MHz
1clock+15
Phase-Locked Loop Characteristics
tacq 139.264MHz
139.264MHz
tjt 139.264MHz
139.264MHz
17.408MHz crystal
MAX
1.7
55
3.3
4.5
9
1clock+20
5
±5
.15%
6
UNITS
ns
%
ns
ns
ns
ns
µs
% of
center freq.
UIp-p
ppm
5

5 Page










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