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PDF ICS1890 Data sheet ( Hoja de datos )
| Número de pieza | ICS1890 | |
| Descripción | 10Base-T/100Base-TX Integrated PHYceiver | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ICS1890 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Integrated
Circuit
Systems, Inc.
ICS1890
10Base-T/100Base-TX Integrated PHYceiver
General Description
The ICS1890 is a fully integrated physical layer device
supporting 10 and 100Mb/s CSMA/CD Ethernet applications.
DTE (adapter cards or motherboards), switching hub, repeater
and router applications are fully supported. The ICS1890
is compliant with the ISO/IEC 8802-3 Ethernet standard
for 10 and 100Mb/s operation.A Media Independent Interface
allowing direct chip-to-chip connection, motherboard-to-
daughterboard connection or connection via an AUI-like
cable is provided. A station management interface is
provided to enable command information and status
information exchange. The ICS1890 interfaces directly to
transmit and receive isolation transformers and can support
shielded twisted pair (STP) and unshielded twisted pair
(UTP) category 5 cables up to 105 meters. Operation in half
duplex or full duplex modes at either 10 or 100 Mbps
speeds is possible with control by Auto-Negotiation or
manual selection. By employing Auto-Negotiation the
technology capabilities of the remote link partner may be
determined and operation automatically adjusted to the
highest performance common operating mode.
Block Diagram
Features
One chip integrated physical layer
All CMOS, Low power design (<200mA max)
Small footprint 64-pin 14mm 2 QFP package
ISO/IEC 8802-3 CSMA/CD compliant
Media Independent Interface (MII)
Alternate 100M stream and 10M 7-wire serial
interfaces provided
10Base-TX Half & Full Duplex
100Base-TX Half & Full Duplex
Fully integrated TP-PMD including Stream
Cipher Scrambler, MLT-3 encoder, Adaptive
Equalization, and Baseline Wander Correction
Circuitry
ICS1890RevG 10/21/97
PHYceiver and QuickPoll are trademarks of Integrated
Circuit Systems, Inc. Patents pending.
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
1 page  
ICS1890
The ICS1890 is designed to allow hot insertion of an MII
cable into a MAC MII port. During the power-up phase, the
ICS1890 will isolate the MII and the Twisted Pair Transmit
signal pair
100M Stream Interface
The 100M Stream Interface is an alternative parallel interface
between the PHY and MAC/Repeater than the standard MII
Data interface. The Stream Interface provides a lower level
interface and, therefore, lower bit delay than the standard MII
Data Interface.
This interface is selected by setting the MII/SI pin to STREAM
INTERFACE mode and by setting the 10/100SEL pin to 100
mode.
The Stream Interface bypasses the Physical Coding Sublayer
(PCS) and provides a direct unscrambled, unframed 5-bit
interface to the Physical Media Access (PMA) layer.
The Stream Interface consists of a 14 signal interface: STCLK,
STD[4:0], SRCLK, SRD[4:0], SCRS, SD.
Data is exchanged between the MAC and PHY using 5-bit
unframed code groups at 25 MHz clock rate.
The Stream Interface provides a CRS signal by continuing to
use the logic that is bypassed by this interface. This gives a
carrier indication faster than is possible from the MAC/Repeater
since the bits are examined serially as soon as they enter the
PHY.
The pins have the following mapping:
MII Stream
TXCLK
TXEN
TXER
TXD3
TXD2
TXD1
TXD0
STCLK
(1)
STD4
STD3
STD2
STD1
STD0
RXCLK
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
SRCLK
(2)
SRD4
SRD3
SRD2
SRD1
SRD0
CRS
COL
LSTA
SCRS
(3)
SD
(1) 100Base-TX is a continuous transmission system and the
MAC/Repeater is responsible for sourcing IDLE symbols
when it is not transmitting data when using the Stream Interface.
(2) Since data is not framed when this interface is used, RXDV
has no meaning.
Since only the Stream Interface or the MII Interface is active
at once, it is possible to share the MII Data interface pins for
Stream Interface functionality.
(3) Since the MAC/Repeater is responsible for sourcing both
active and idle data, the PHY can not tell when it is transmitting
in the traditional sense, so no collisions can be detected.
Other mode configuration pins behave identically regardless
of which data interface is used.
5
5 Page 
ICS1890
4B5B Encoding (including invalid test mode coding)
Symbol
0
1
2
3
4
5
6
7
I
J
K
T
R
H
V
V
Meaning
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Idle
SSD
SSD
ESD
ESD
Error
Invalid
Invalid
4B Code
3210
0000
0001
0010
0011
0100
0101
0110
0111
5B Code
43210
11110
01001
10100
10101
01010
01011
01110
01111
undefined
0101
0101
undefined
undefined
undefined
undefined
undefined
11111
11000
10001
01101
00111
00100
00000
00001
Symbol
8
9
A
B
C
D
E
F
V
V
V
V
V
V
V
V(S)
Meaning
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
4B Code
3210
1000
1001
1010
1011
1100
1101
1110
1111
5B Code
43210
10010
10011
10110
10111
11010
11011
11100
11101
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
00010
00011
00101
00110
01000
01100
10000
11001
Invalid Error Code Test (TXER asserted)
I Idle
J SSD
K SSD
T ESD
R ESD
H Error
V Invalid
V Invalid
1111
1110
1011
1001
0111
0100
0000
0001
11111
11000
10001
01101
00111
00100
00000
00001
V
V
V
V
V
V
V
V(S)
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
0010
0011
0101
0110
1000
1010
1100
1101
00010
00011
00101
00110
01000
01100
10000
11001
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ICS1890.PDF ] | |
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