|
|
PDF ICS1893 Data sheet ( Hoja de datos )
| Número de pieza | ICS1893 | |
| Descripción | 3.3-V 10Base-T/100Base-TX Integrated PHYceiver | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ICS1893 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Integrated Circuit Systems, Inc.
ICS1893
Document Type: Data Sheet
Document Stage: Release
3.3-V 10Base-T/100Base-TX Integrated PHYceiver™
General
The ICS1893 is a low-power, physical-layer device (PHY)
that supports the ISO/IEC 10Base-T and 100Base-TX
Carrier-Sense Multiple Access/Collision Detection
(CSMA/CD) Ethernet standards. The ICS1893 architecture
is based on the ICS1892. The ICS1893 supports managed
or unmanaged node, repeater, and switch applications.
The ICS1893 incorporates digital signal processing (DSP) in
its Physical Medium Dependent (PMD) sublayer. As a result,
it can transmit and receive data on unshielded twisted-pair
(UTP) category 5 cables with attenuation in excess of 24 dB
at 100 MHz. With this ICS-patented technology, the
ICS1893 can virtually eliminate errors from killer packets.
The ICS1893 provides a Serial Management Interface for
exchanging command and status information with a Station
Management (STA) entity.
The ICS1893 Media Dependent Interface (MDI) can be
configured to provide either half- or full-duplex operation at
data rates of 10 MHz or 100 MHz. The MDI configuration
can be established manually (with input pins or control
register settings) or automatically (using the
Auto-Negotiation features). When the ICS1893
Auto-Negotiation sublayer is enabled, it exchanges
technology capability data with its remote link partner and
automatically selects the highest-performance operating
mode they have in common.
Features
• Supports category 5 cables with attenuation in excess of
24 dB at 100 MHz across a temperature range from -5°to
+85°C
• DSP-based baseline wander correction to virtually
eliminate killer packets across temperature range of from
-5°to +85°C
• Low-power, 0.35-micron CMOS (typically 400 mW)
• Single 3.3-V power supply.
• Single-chip, fully integrated PHY provides PCS, PMA,
PMD, and AUTONEG sublayers of IEEE standard
• 10Base-T and 100Base-TX IEEE 802.3 compliant
• Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline wander correction
– Transmit wave shaping and stream cipher scrambler
– MLT-3 encoder and NRZ/NRZI encoder
• Highly configurable design supports:
– Node, repeater, and switch applications
– Managed and unmanaged applications
– 10M or 100M half- and full-duplex modes
– Parallel detection
– Auto-negotiation, with Next Page capabilities
• MAC/Repeater Interface can be configured as:
– 10M or 100M Media Independent Interface
– 100M Symbol Interface (bypasses the PCS)
– 10M 7-wire Serial Interface
• Small Footprint 64-pin Thin Quad Flat Pack (TQFP)
ICS1893 Block Diagram
10/100 MII or
Alternate
MAC/Repeater
Interface
Interface
MUX
MII Serial
Management
Interface
MII
Extended
Register
Set
PCS
• Frame
• CRS/COL
Detection
• Parallel to Serial
• 4B/5B
Low-Jitter
Clock
Synthesizer
Clock
100Base-T
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
10Base-T
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Configuration
and Status
Integrated
Switch
Auto-
Negotiation
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
Power
LEDs and PHY
Address
ICS1893 Rev C 6/6/00
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any information
being relied upon by the customer is current and accurate.
June, 2000
1 page  
ICS1893 - Release
Table of Contents
Table of Contents
Section
8.5
8.5.1
8.5.2
8.5.3
8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.7
8.7.1
8.7.2
8.7.3
8.7.4
8.7.5
8.8
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.9
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.10
8.10.1
8.10.2
8.10.3
8.10.4
8.10.5
Title
Page
Register 3: PHY Identifier Register ........................................................................ 74
OUI bits 19-24 (bits 3.15:10) .................................................................................. 74
Manufacturer's Model Number (bits 3.9:4) ............................................................. 75
Revision Number (bits 3.3:0) ................................................................................. 75
Register 4: Auto-Negotiation Register ................................................................... 76
Next Page (bit 4.15) ............................................................................................... 76
IEEE Reserved Bit (bit 4.14) .................................................................................. 77
Remote Fault (bit 4.13) .......................................................................................... 77
IEEE Reserved Bits (bits 4.12:10) ......................................................................... 77
Technology Ability Field (bits 4.9:5) ....................................................................... 78
Selector Field (Bits 4.4:0) ....................................................................................... 79
Register 5: Auto-Negotiation Link Partner Ability Register .................................... 80
Next Page (bit 5.15) ............................................................................................... 80
Acknowledge (bit 5.14) .......................................................................................... 81
Remote Fault (bit 5.13) .......................................................................................... 81
Technology Ability Field (bits 5.12:5) ..................................................................... 81
Selector Field (bits 5.4:0) ....................................................................................... 81
Register 6: Auto-Negotiation Expansion Register .................................................. 82
IEEE Reserved Bits (bits 6.15:5) ........................................................................... 82
Parallel Detection Fault (bit 6.4) ............................................................................. 83
Link Partner Next Page Able (bit 6.3) .................................................................... 83
Next Page Able (bit 6.2) ......................................................................................... 83
Page Received (bit 6.1) ......................................................................................... 83
Link Partner Auto-Negotiation Able (bit 6.0) .......................................................... 83
Register 7: Auto-Negotiation Next Page Transmit Register ................................... 84
Next Page (bit 7.15) ............................................................................................... 85
IEEE Reserved Bit (bit 7.14) .................................................................................. 85
Message Page (bit 7.13) ........................................................................................ 85
Acknowledge 2 (bit 7.12) ....................................................................................... 85
Toggle (bit 7.11) ..................................................................................................... 85
Message Code Field / Unformatted Code Field (bits 7.10:0) ................................. 85
Register 8: Auto-Negotiation Next Page Link Partner Ability Register ................... 86
Next Page (bit 8.15) ............................................................................................... 87
IEEE Reserved Bit (bit 8.14) .................................................................................. 87
Message Page (bit 8.13) ........................................................................................ 87
Acknowledge 2 (bit 8.12) ....................................................................................... 87
Message Code Field / Unformatted Code Field (bits 8.10:0) ................................. 87
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
5
June, 2000
5 Page 
ICS1893 - Release
Chapter 1 Abbreviations and Acronyms
Chapter 1 Abbreviations and Acronyms
Table 1-1 lists and interprets the abbreviations and acronyms used throughout this data sheet.
Table 1-1. Abbreviations and Acronyms
Abbreviation /
Acronym
Interpretation
4B/5B
4-Bit / 5-Bit Encoding/Decoding
ANSI
American National Standards Institute
CMOS
complimentary metal-oxide semiconductor
CSMA/CD
Carrier Sense Multiple Access with Collision Detection
CW Command Override Write
DSP
digital signal processing
ESD
End-of-Stream Delimiter
FDDI
Fiber Distributed Data Interface
FLL frequency-locked loop
FLP Fast Link Pulse
IDL A ‘dead’time on the link following a 10Base-T packet, not to be confused with idle
IEC International Electrotechnical Commission
IEEE
Institute of Electrical and Electronic Engineers
ISO International Standards Organization
LH Latching High
LL Latching Low
LMX
Latching Maximum
MAC
Media Access Control
Max.
maximum
Mbps
Megabits per second
MDI Media Dependent Interface
MF Management Frame
MII Media Independent Interface
Min. minimum
MLT-3
Multi-Level Transition Encoding (3 Levels)
N/A Not Applicable
NLP Normal Link Pulse
No. Number
NRZ
Not Return to Zero
NRZI
Not Return to Zero, Invert on one
OSI Open Systems Interconnection
ICS1893 Rev C 6/6/00
Copyright © 2000, Integrated Circuit Systems, Inc.
All rights reserved.
11
June, 2000
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ICS1893.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ICS1890 | 10Base-T/100Base-TX Integrated PHYceiver | Integrated Circuit Systems |
| ICS1892 | 10Base-T/100Base-TX Integrated PHYceiver | Integrated Circuit Systems |
| ICS1893 | 3.3-V 10Base-T/100Base-TX Integrated PHYceiver | Integrated Circuit Systems |
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM | Integrated Circuit Systems |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |